Generate an FPGA design-health scorecard from Vivado timing, utilization, power, and congestion metrics.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill qor-report
Please help me install this Agent Skill. Skill: qor-report Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/qor-report Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill qor-report
This skill eliminates the manual, fragmented process of gathering FPGA design metrics by providing a consolidated, one-page health report that grades timing, area, power, and congestion.
Invoke the qor-report skill to generate a comprehensive design health scorecard for the currently open Vivado project.
High-intent search queries and answers about installing and using this skill.
To generate an FPGA design health scorecard, use a skill that analyzes timing, utilization, power, congestion, and rule-cleanliness metrics from synthesized or implemented Vivado designs. This provides an objective assessment of design readiness for signoff.
FPGA timing and utilization analysis for signoff evaluates six critical axes: timing, utilization, power, congestion, and DRC/methodology rule-cleanliness. These metrics are aggregated to classify design health as PASS, MARGINAL, or FAIL based on current tool evidence.
Yes, an active SynthPilot MCP connection is required to evaluate Vivado implementation status. The connection executes read-only tool queries to gather metrics and synthesize a consolidated report.
Yes, automated scorecarding can identify FPGA design readiness before tapeout by generating an objective snapshot of implementation status. It uses a standardized rubric to classify design health as PASS, MARGINAL, or FAIL.
The best way to consolidate fragmented FPGA design metrics is to use an automated scorecarding skill that aggregates data across timing, area, power, and congestion into a one-page health report.
LNC0831...
btabaskaAutomate multi-gate quality validation on generated code with parallel checks.
adeleempurpled290Guide selection of Vivado implementation directives and optimization strategies for FPGA designs.
adeleempurpled290Interpret Vivado design analysis reports and resolve timing closure issues.
