Automates RTL linting and methodology violation triage via SynthOol tools.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill lint-triage
Please help me install this Agent Skill. Skill: lint-triage Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/lint-triage Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill lint-triage
This skill solves the problem of overwhelming, unorganized RTL linting warnings by providing a structured, methodology-driven approach to triage violations into actionable fixes, documented waivers, or human-review items.
Invoke the lint-triage skill to perform a full RTL quality review and generate a triage report for the current project.
High-intent search queries and answers about installing and using this skill.
RTL linting triage categorizes violations into actionable fixes, documented waivers, or human-review items using a structured methodology. This organizes overwhelming warnings before FPGA synthesis sign-off.
Detecting unintended latches in Vivado requires synthesis-aware analysis on the synthesized netlist. This methodology evaluates latch inference, FSM health, and clock domain crossing violations.
Yes, an active Vivado Tcl server connection and an open synthesized design are required to perform full methodology-stage analysis. This environment enables deep linting checks on the netlist.
The best way to classify FPGA coding style violations is a systematic triage that evaluates width mismatches and style issues against design best practices. This structures violations into fix, waive, or ask buckets.
No, full methodology-stage analysis requires an open synthesized design. An active Vivado Tcl server connection and synthesized netlist are necessary to execute deep checks like latch inference.
LNC0831Generate an FPGA design-health scorecard from Vivado timing, utilization, power, and congestion metrics.
chuanseng-ngConvert C/C++ algorithms to synthesisable RTL with HLS directives and equivalence verification.
LNC0831Orchestrate iterative timing closure for FPGA designs in Vivado.
VoDaiLoczAutomate linting and static analysis of code in CI pipelines.
