Audit and resolve clock-domain-crossing risks in FPGA netlists.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill cdc-audit
Please help me install this Agent Skill. Skill: cdc-audit Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/cdc-audit Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill cdc-audit
This skill solves the critical challenge of identifying and resolving metastability risks in FPGA designs where signals cross between asynchronous clock domains, preventing silent hardware failures that standard timing analysis often misses.
Invoke the cdc-audit skill to perform a full structural analysis and generate a resolution report for the current design.
High-intent search queries and answers about installing and using this skill.
To fix metastability risks in FPGA clock domain crossings, perform structural CDC analysis on synthesized netlists to classify crossings and apply safe synchronization fixes, preventing silent hardware failures that standard timing analysis misses.
To audit asynchronous clock boundaries in Vivado, you need an active SynthPilot MCP connection to perform structural linting and timing interaction analysis on elaborated netlists, verifying that async FIFO or handshake logic is truly safe.
The best way to verify async FIFO and handshake logic for metastability safety is structural CDC linting on synthesized netlists, which classifies clock crossings by structure and applies a rigorous resolution workflow prioritizing RTL improvements over masking constraints.
Yes, clock domain crossing analysis operates on both synthesized and elaborated netlists in Vivado, requiring an active SynthPilot MCP connection to perform structural linting and ensure metastability safety across asynchronous boundaries.
Standard timing analysis misses metastability issues because it does not structurally classify clock domain crossings or apply targeted synchronization fixes to asynchronous boundaries, leaving silent hardware failures undetected until intermittent behavior occurs.
You should use structural RTL improvements instead of masking constraints when resolving clock domain crossings, as a rigorous resolution workflow prioritizes the smallest safe structural fix to ensure true metastability safety rather than masking timing violations.
LNC0831Generate an FPGA design-health scorecard from Vivado timing, utilization, power, and congestion metrics.
KishoreDamamSelect safe clock-domain-crossing structures for asynchronous signal transfers.
chuanseng-ngAutomate ASIC RTL adaptation, synthesis, and bring-up for FPGA prototypes.
babywormAnalyzes clock domain crossings and generates CDC reports plus SDC constraint files.
