Generate FPGA bitstreams and program JTAG or SPI/BPI flash memory devices.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill bitstream-program
Please help me install this Agent Skill. Skill: bitstream-program Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/bitstream-program Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill bitstream-program
This skill removes the manual complexity of FPGA deployment by orchestrating the transition from a routed design to live silicon, ensuring all sign-off gates are met before programming.
Invoke the bitstream-program skill to generate a bitstream and flash the connected FPGA board for non-volatile boot.
High-intent search queries and answers about installing and using this skill.
FPGA bitstream generation and JTAG programming are automated by orchestrating the end-to-end workflow from routed design sign-off to hardware deployment. This workflow validates route status, DRCs, and timing closure before generating the bitstream and programming the device.
Flashing an FPGA bitstream to non-volatile SPI or BPI flash memory is handled through flexible programming options that support production boot. The workflow connects to the hardware server and programs the flash memory while verifying boot-mode requirements.
Vivado Tcl and a SynthPilot MCP server connection are required to program an FPGA board. Physical access to the target hardware is also necessary to complete the transition from routed implementation to live silicon deployment.
Validation checks required before deploying a bitstream to FPGA hardware include automatic verification of route status, design rule checks (DRCs), and timing closure. These sign-off gates ensure the routed design meets all requirements before any hardware action occurs.
Volatile JTAG downloads for FPGA bench testing are fully supported alongside non-volatile flash programming. This allows you to choose flexible programming options depending on whether you need temporary debug testing or permanent production boot deployment.
Deploying a bitstream to a Zynq SoC for production boot involves generating the bitstream, connecting to the hardware server, and programming the flash memory. The process automatically verifies all sign-off gates and boot-mode requirements before deployment.
LNC0831Automates RTL linting and methodology violation triage via SynthOol tools.
LNC0831Insert Integrated Logic Analyzers and execute hardware debug cycles on FPGA silicon.
LNC0831Orchestrate the Xilinx FPGA build flow from RTL simulation to bitstream generation.
konosubakonoakuaConfigure and troubleshoot Vivado debugging cores for FPGA designs.
