Generate Vivado XDC constraints from KiCad netlists with pin-bank mapping and IO standards.
npx skills add https://github.com/pjy4617/pjy-claude-skill --skill kicad-xdc
Please help me install this Agent Skill. Skill: kicad-xdc Source: https://github.com/pjy4617/pjy-claude-skill/tree/main/plugins/vivado/skills/kicad-xdc Command: npx skills add https://github.com/pjy4617/pjy-claude-skill --skill kicad-xdc
KiCad 회로도에서 Vivado XDC 제약 파일을 자동으로 생성하여 핀 배치 매핑, IO표준 설정 및 타이밍 제약 작성을 간소화합니다. 이 스킬은 KiCad 넷리스트를 기반으로 빠르게 제약 파일을 생성하고, pin-reviewer를 통해 검증하는 워크플로우를 제공합니다.
Run the KiCad netlist through the skill to generate an XDC file and review it with the pin-reviewer.
High-intent search queries and answers about installing and using this skill.
To generate Vivado XDC constraints from a KiCad netlist, you need a boards.json file defining bank definitions and a net-patterns file to classify signals, which the tool uses to map FPGA pins and assign IO standards.
Yes, you can automatically map FPGA pins to banks and assign IO standards by processing your KiCad 8.0+ netlist alongside the required boards.json and net-patterns files to estimate configurations.
You need a KiCad netlist, a boards.json file describing bank definitions, and a net-patterns file to classify signals, which together allow the tool to produce a constraints file and a review report.
Yes, the workflow creates timing constraints within the generated XDC file and includes a validation step using a separate reviewer component to ensure pin-mapping and IO standard accuracy.
The best way to validate automatically generated XDC constraints is by using the integrated pin-reviewer workflow, which reviews the output constraints file and produces a dedicated report for verification.
Yes, KiCad 8.0 or later is required because the tool processes netlists from these newer KiCad designs to accurately map FPGA pins, assign IO standards, and create the necessary timing constraints.
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