kicad-xdc

Generate Vivado XDC constraints from KiCad netlists with pin-bank mapping and IO standards.

Updated Mar 17, 2026

Search Tags:#kicad #fpga #pin-mapping #vivado #xdc #io-standard

Ready to run

npx skills add https://github.com/pjy4617/pjy-claude-skill --skill kicad-xdc

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: kicad-xdc
Source: https://github.com/pjy4617/pjy-claude-skill/tree/main/plugins/vivado/skills/kicad-xdc
Command: npx skills add https://github.com/pjy4617/pjy-claude-skill --skill kicad-xdc

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

KiCad 회로도에서 Vivado XDC 제약 파일을 자동으로 생성하여 핀 배치 매핑, IO표준 설정 및 타이밍 제약 작성을 간소화합니다. 이 스킬은 KiCad 넷리스트를 기반으로 빠르게 제약 파일을 생성하고, pin-reviewer를 통해 검증하는 워크플로우를 제공합니다.

Core Features & Use Cases

KiCad 넷리스트로부터 Vivado XDC를 자동 생성합니다.
핀-뱅크 매핑 및 IO STANDARD의 기본 추정을 수행합니다.
제약 파일 생성 후 pin-reviewer로 검증하는 엔드투엔드 워크플로우의 대표 사례를 지원합니다.

Quick Start

Run the KiCad netlist through the skill to generate an XDC file and review it with the pin-reviewer.

Frequently Asked Questions about kicad-xdc

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I generate Vivado XDC constraints from a KiCad netlist?▼

To generate Vivado XDC constraints from a KiCad netlist, you need a boards.json file defining bank definitions and a net-patterns file to classify signals, which the tool uses to map FPGA pins and assign IO standards.

Can I automatically map FPGA pins to banks and set IO standards using KiCad?▼

Yes, you can automatically map FPGA pins to banks and assign IO standards by processing your KiCad 8.0+ netlist alongside the required boards.json and net-patterns files to estimate configurations.

What files do I need to create XDC constraints from KiCad for my FPGA design?▼

You need a KiCad netlist, a boards.json file describing bank definitions, and a net-patterns file to classify signals, which together allow the tool to produce a constraints file and a review report.

Does this KiCad to Vivado XDC workflow support timing constraints and validation?▼

Yes, the workflow creates timing constraints within the generated XDC file and includes a validation step using a separate reviewer component to ensure pin-mapping and IO standard accuracy.

What is the best way to validate automatically generated XDC constraints from KiCad?▼

The best way to validate automatically generated XDC constraints is by using the integrated pin-reviewer workflow, which reviews the output constraints file and produces a dedicated report for verification.

Is KiCad 8.0 or later required to map FPGA pins to Vivado XDC?▼

Yes, KiCad 8.0 or later is required because the tool processes netlists from these newer KiCad designs to accurately map FPGA pins, assign IO standards, and create the necessary timing constraints.