pin-review

Pin placement review validates XDC constraints and port mappings in Vivado FPGA projects to prevent hardware damage. It enforces a seven-category checklist covering port matching, IO standard consistency, timing constraints, and safe power sequencing with a PASS/WARN/FAIL rubric.

An IOSTANDARD consistency check verifies that all FPGA pin assignments in the XDC file use matching IO standards, ensuring safe power sequencing and preventing board-level electrical mismatches. It forms one of seven review categories evaluated during the pin layout audit.

Yes, automated pin mapping checks review Vivado FPGA projects by validating 1:1 port mapping, pin assignments, and board compatibility. The review process delegates execution to a specialized pin-reviewer agent that applies standardized checklist criteria to identify mismatches.

The best way to verify timing constraints and functional pin assignments is applying a structured review rubric. This approach evaluates seven categories including timing constraints, functional pin checks, and board compatibility, yielding clear PASS, WARN, or FAIL results for each constraint.

A FAIL on IO standard consistency occurs when XDC constraints specify conflicting voltage standards for connected pins. The review rubric detects mismatches in IO standard configurations and unsafe power sequencing conditions that risk hardware damage, flagging them for correction.

Yes, a complete XDC file with defined port mappings and IO standard assignments is required to perform a pin placement review. The review evaluates seven categories including pin assignment, timing constraints, and board compatibility, all of which depend on accurate XDC constraint definitions.