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vivado-sim

Guide Vivado simulation workflows for RTL, post-synthesis, and post-implementation verification.

2|Updated May 6, 2026
Search Tags:#simulation#timing#rtl#sdf#vivado#xsim#glbl
One-click install
npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vivado-sim-konosubakonoakua
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-sim
Source: https://github.com/konosubakonoakua/xilinx-skills/tree/main/vivado-sim
Command: npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vivado-sim-konosubakonoakua

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill provides a comprehensive guide to planning, executing, and debugging Vivado simulations, covering RTL behavioral simulations, post-synthesis timing, and post-implementation timing checks, with toolchains like xsim and third-party simulators, to accelerate verification workflows.

Core Features & Use Cases

  • RTL behavioral simulation for functional validation.
  • Post-synthesis functional and timing simulations to verify netlists.
  • Post-implementation timing simulations with SDF annotations and glbl.v support.
  • xsim-based engineering workflows (compile, elaborate, simulate) with project-mode and script-driven automation.
  • Third-party simulator integration (Questa, ModelSim, VCS, Xcelium, Riviera, Active-HDL) including compile_simlib, export_simulation, and launch_simulation.
  • SAIF/VCD power profiling via open_saif, log_saif, and read_saif for report_power.

Quick Start

Run an RTL behavioral simulation with xsim following the engineer's guide and save the waveform results

Frequently Asked Questions about vivado-sim

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I run a post-implementation timing simulation in Vivado with SDF annotation?▼

Post-implementation timing simulation in Vivado requires SDF annotation and glbl.v support. You can execute this using launch_simulation commands aligned with UG900 v2025.2 syntax to validate designs and analyze timing performance.

What is the xsim three-step flow for RTL behavioral simulation?▼

The xsim three-step flow consists of compile, elaborate, and simulate stages for RTL behavioral simulation. This workflow supports project-mode usage and script-driven automation to achieve reproducible functional validation runs.

Can I use third-party simulators like Questa or VCS with Vivado?▼

Vivado supports third-party simulator integration with Questa, ModelSim, VCS, Xcelium, Riviera, and Active-HDL. You can use compile_simlib, export_simulation, and launch_simulation commands to prepare and execute simulation libraries across these tools.

How do I generate a SAIF file for power profiling in Vivado simulation?▼

SAIF power profiling uses open_saif, log_saif, and read_saif commands during simulation to capture switching activity. You then pass this data to report_power for accurate power analysis of your FPGA design.

Why do I need glbl.v for post-synthesis functional simulations?▼

glbl.v is required for post-synthesis and post-implementation simulations to properly initialize the Vivado simulation environment and global signals. It ensures the netlist timing checks and SDF annotations function correctly during verification.

What is the best way to automate Vivado simulation workflows for reproducible runs?▼

Script-driven automation using xsim commands like write_verilog, write_sdf, and launch_simulation provides reproducible Vivado simulation workflows. This approach eliminates manual GUI steps and ensures consistent RTL, post-synthesis, and post-implementation verification runs.

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