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vivado-sim

Select and execute Vivado simulation workflows for functional verification and timing closure.

27|5|Updated Apr 19, 2026
Search Tags:#simulation#fpga#vivado#xsim#saif#timing simulation#third-party simulator
One-click install
npx skills add https://github.com/adeleempurpled290/FPGA-Agent-skills --skill vivado-sim-adeleempurpled290
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-sim
Source: https://github.com/adeleempurpled290/FPGA-Agent-skills/tree/main/vivado-sim
Command: npx skills add https://github.com/adeleempurpled290/FPGA-Agent-skills --skill vivado-sim-adeleempurpled290

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill eliminates the steep learning curve of Vivado's complex simulation ecosystem, helping you select the correct simulation stage for your verification goals, use xsim and third-party simulators properly, and quickly debug common simulation issues without sifting through lengthy official documentation.

Core Features & Use Cases

  • Simulation Flow Selection: Clear guidance on when to use behavioral, post-synthesis, or post-implementation timing simulation for functional verification, synthesis correctness checks, or timing closure validation.
  • xsim Command Reference: Complete syntax for the xvlog/xvhdl/xelab/xsim three-step flow, Vivado Project Mode launch_simulation commands, and interactive debug tools like add_force, add_wave, and breakpoints.
  • Third-Party Simulator Integration: Step-by-step setup for Questa, ModelSim, VCS, Xcelium, Riviera-PRO, and Active-HDL using compile_simlib and export_simulation.
  • Power Analysis Support: Guidance for collecting SAIF or VCD data during simulation to feed into Vivado's report_power workflow for accurate power estimation.
  • Use Case: If your post-synthesis simulation produces mismatched results compared to RTL simulation, use this Skill to quickly identify whether the issue stems from synthesis errors, missing glbl.v files, or incorrect SDF annotation.

Quick Start

Use the vivado-sim skill to troubleshoot inconsistent results between your RTL behavioral simulation and post-synthesis netlist simulation, and get step-by-step guidance to isolate the root cause.

Frequently Asked Questions about vivado-sim

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
Why does my post-synthesis simulation produce mismatched results compared to RTL behavioral simulation in Vivado?▼

Post-synthesis simulation mismatches often stem from synthesis errors, missing glbl.v files, or incorrect SDF back-annotation. You can isolate the root cause by checking your Vivado simulation flow selection and validating timing simulation netlist generation.

How do I run the xsim three-step flow for FPGA simulation in Vivado?▼

The xsim three-step simulation flow uses xvlog or xvhdl for compilation, xelab for elaboration, and xsim for execution. This Skill provides complete command syntax and project property configuration for functional verification.

Can I use third-party simulators like Questa, ModelSim, or VCS with Vivado?▼

Yes, Vivado integrates with Questa, ModelSim, VCS, Xcelium, Riviera-PRO, and Active-HDL. Setup requires using compile_simlib to compile simulation libraries and export_simulation to generate the necessary scripts.

How do I collect SAIF or VCD power data during a Vivado timing simulation?▼

To collect SAIF or VCD power data during simulation, configure your xsim or third-party simulator flow to output switching activity files. These files feed directly into Vivado's report_power workflow for accurate power estimation.

When should I use behavioral, post-synthesis, or post-implementation timing simulation?▼

Use behavioral simulation for RTL functional verification, post-synthesis for synthesis correctness checks, and post-implementation timing simulation for timing closure analysis. Selecting the correct Vivado simulation stage depends on your specific validation goals.

What is the best way to debug FPGA timing simulation issues using xsim interactive tools?▼

Debugging timing simulation in xsim utilizes interactive tools like add_force, add_wave, and breakpoints. This Skill offers debugging guidance aligned with AMD Vivado UG900 v2025.2 to help you quickly resolve netlist issues.

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