Agent Skills by adeleempurpled290
Showing 8 vetted skills indexed across 1 GitHub repositories.
adeleempurpled29027
vitis-hls-synthesis
Convert C/C++ HLS designs to optimized RTL for AMD FPGAs.
Community
Intermediate
adeleempurpled29027
vivado-sim
Select and execute Vivado simulation workflows for functional verification and timing closure.
Community
Intermediate
adeleempurpled29027
vivado-tcl
Generate and execute Vivado TCL scripts for FPGA design workflows.
Community
Intermediate
adeleempurpled29027
vivado-impl
Guide selection of Vivado implementation directives and optimization strategies for FPGA designs.
Community
Advanced
adeleempurpled29027
vivado-constraints
Generate XDC/SDC constraints for AMD Vivado FPGA designs.
Community
Advanced
adeleempurpled29027
vivado-debug
Configure ILA and VIO debug cores for AMD Vivado FPGA designs.
Community
Intermediate
adeleempurpled29027
vivado-analysis
Interpret Vivado design analysis reports and resolve timing closure issues.
Community
Advanced
adeleempurpled29027
vivado-synth
Select Vivado synthesis directives, attributes, and options for FPGA design constraints.
Community
Advanced