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vivado-debug

Configure ILA and VIO debug cores for AMD Vivado FPGA designs.

27|5|Updated Apr 19, 2026
Search Tags:#vivado#vio#ila#jtag-to-axi#fpga debugging#hardware programming#debug cores
One-click install
npx skills add https://github.com/adeleempurpled290/FPGA-Agent-skills --skill vivado-debug-adeleempurpled290
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-debug
Source: https://github.com/adeleempurpled290/FPGA-Agent-skills/tree/main/vivado-debug
Command: npx skills add https://github.com/adeleempurpled290/FPGA-Agent-skills --skill vivado-debug-adeleempurpled290

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

FPGA developers and hardware engineers face significant challenges when debugging implemented Vivado designs, including configuring specialized debug cores, programming FPGA/SoC devices, and resolving common errors like undetected debug hubs, timing violations from debug logic, and debug core connectivity issues.

Core Features & Use Cases

  • Debug Core Configuration Guidance: Covers ILA (Integrated Logic Analyzer) setup including trigger strategies, data depth selection, cross-triggering, and capture control; VIO (Virtual I/O) usage for real-time signal monitoring and control; and JTAG-to-AXI Master configuration for AXI register access.
  • Hardware Programming Support: Provides step-by-step flows for programming 7 Series, UltraScale, UltraScale+, and Versal adaptive SoC devices, plus SVF file generation for offline programming scenarios.
  • Troubleshooting & Timing Mitigation: Includes solutions for common debug errors, debug clock requirement guidelines, and step-by-step timing impact mitigation for debug core additions.
  • Use Case: A developer working on a Zynq-7000 based design can use this skill to insert an ILA core via netlist insertion, configure advanced triggers to capture a rare AXI bus error, program the device, and resolve a debug hub detection issue caused by an unstable debug clock.

Quick Start

Use the vivado-debug skill to configure an ILA core for your synthesized design, set up advanced trigger conditions to capture a specific bus transaction, and program your FPGA device to test the debug flow.

Frequently Asked Questions about vivado-debug

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I configure an ILA core in Vivado to capture a specific AXI bus transaction?▼

Configure the ILA core in Vivado by applying the mark_debug probing flow to your synthesized netlist, then set advanced trigger conditions and data depth to capture the specific AXI bus transaction accurately.

Why is my Vivado debug hub not detected during hardware programming?▼

A Vivado debug hub is often not detected due to an unstable debug clock or connectivity issues; verify debug clock requirements and JTAG connection stability to resolve the detection error.

Can I use JTAG-to-AXI Master to access AXI registers in UltraScale+ designs?▼

Yes, JTAG-to-AXI Master works with UltraScale+ designs to generate AXI transactions for direct register access, enabling in-system debugging without requiring a full processor system.

What is the best way to mitigate timing violations caused by added debug cores in FPGA designs?▼

The best way to mitigate timing violations from FPGA debug cores is to follow debug timing impact mitigation guidelines, ensuring debug clock domains are properly constrained and isolated from critical functional logic paths.

Does this Vivado debugging guidance cover SVF file generation for offline programming?▼

Yes, Vivado debugging guidance covers SVF file generation to support offline programming scenarios for 7 Series, UltraScale, UltraScale+, and Versal adaptive SoC devices when direct JTAG is unavailable.

How do I set up a Versal AXI4 Debug Hub for in-system debugging?▼

Set up a Versal AXI4 Debug Hub by configuring the debug hub within your Vivado implementation, verifying debug clock connectivity, and using TCL commands in Hardware Manager to establish the scan chain.

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