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vivado-impl

Guide FPGA Vivado implementation decisions for timing closure and resource optimization.

156|19|Updated Mar 27, 2026
Search Tags:#routing#implementation#optimization#vivado#tcl#congestion#timing-closure
One-click install
npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-impl-shinei-nouzen-arch
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-impl
Source: https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills/tree/main/vivado-impl
Command: npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-impl-shinei-nouzen-arch

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

The Vivado implementation decision guide helps engineers pick the right combination of implementation directives and flows to achieve timing closure and congestion resilience across placement and routing phases.

Core Features & Use Cases

  • Strategy tables for opt_design, place_design, phys_opt_design, route_design, and incremental implementation, plus QoR interpretation guidelines.
  • Pre-defined implementation strategies (Performance, Congestion, Area) and ECO flow patterns to standardize repeatable results.
  • Guidance on interpreting timing reports, QoR suggestions, and how to apply post-place and post-route optimizations for Versal and 7-series/UltraScale devices.

Quick Start

Start with opt_design, then place_design, then phys_opt_design, and finally route_design using recommended defaults or QoR-guided options to resolve timing or congestion.

Frequently Asked Questions about vivado-impl

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I resolve congestion and achieve timing closure during Vivado implementation?▼

To achieve timing closure and resolve congestion during Vivado implementation, apply pre-defined strategy templates across opt_design, place_design, and route_design, using QoR interpretation guidelines to select the correct directives for your specific Versal or UltraScale device.

What is the best sequence for running Vivado implementation commands to optimize routing?▼

The best sequence to optimize routing starts with opt_design, followed by place_design, then phys_opt_design, and finally route_design, applying QoR-guided options or recommended defaults to systematically address timing or congestion issues.

When do I need to use incremental implementation and ECO flows in Vivado?▼

You need incremental implementation and ECO flows in Vivado to standardize repeatable results after minor design changes, utilizing policy tables and strategy templates to preserve previous placement and routing while applying post-route optimizations.

How do I interpret timing reports to apply post-place and post-route optimizations in Vivado?▼

Interpret timing reports using QoR suggestions to guide post-place and post-route optimizations, selecting specific phys_opt_design and route_design directives to target negative slack paths and improve overall design performance.

Does this implementation guidance apply to both Versal and 7-series FPGA devices?▼

Yes, the implementation guidance applies to both Versal and 7-series or UltraScale devices, providing tailored strategies for Performance, Congestion, and Area optimization across the different FPGA architectures.

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