dse-loop

Automate iterative design space exploration for computer architecture and EDA.

Updated Jul 6, 2026
One-click install
npx skills add https://github.com/caw111/2026-SoftwareCup --skill dse-loop-caw111
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: dse-loop
Source: https://github.com/caw111/2026-SoftwareCup/tree/main/.agents/skills/dse-loop
Command: npx skills add https://github.com/caw111/2026-SoftwareCup --skill dse-loop-caw111

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires python, and includes scripts (resource) components.

What problem does it solve?

This Skill automates the design space exploration process in computer architecture and Electronic Design Automation (EDA), streamlining the iterative optimization of parameters for achieving design objectives.

Core Features & Use Cases

  • Iterative Parameter Tuning: Automatically runs programs, analyzes results, tunes parameters, and iterates until objectives are met or a timeout is reached.
  • Flexible Use Cases: Ideal for microarchitecture, synthesis, RTL, compiler flag, placement/routing, formal verification, and memory subsystem optimization.
  • Use Case: For instance, it can be used to optimize cache size, associativity, and pipeline width in a microarchitectural design for maximum IPC or minimum area×delay.

Quick Start

To initiate a design space exploration, use the command: /dse-loop "Run simulation with parameters. Objective: maximize IPC. Timeout: 1h"

Frequently Asked Questions about dse-loop

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate design space exploration for microarchitecture optimization?

Design space exploration works by automatically running programs, analyzing the results, and tuning parameters iteratively until objectives are met or a timeout is reached. This applies to microarchitecture, synthesis, and RTL optimization.

Can I use Python to automate parameter tuning for RTL synthesis and placement?

Yes, Python is required to execute the scripts and analyze results for parameter tuning. You can automate iterative optimization for RTL synthesis, placement, routing, and compiler flags to meet specific design metrics.

What EDA tasks can benefit from iterative design space exploration?

Iterative design space exploration benefits EDA tasks including microarchitecture optimization, synthesis, RTL design, compiler flag tuning, placement and routing, formal verification, and memory subsystem optimization to achieve target design metrics.

How do I optimize cache size and pipeline width for maximum IPC?

You optimize cache size and pipeline width by initiating an automated exploration loop with a command specifying your objective, such as maximizing IPC. The system iterates parameters until the target metric is achieved or the timeout expires.

What are the limitations of automating parameter tuning with design space exploration?

The main limitation is the timeout constraint, as the iterative process stops when the time limit is reached. Additionally, it requires Python to execute scripts and analyze results, meaning your environment must support Python execution.