What problem does it solve? Writing AscendC kernels for Ascend NPU hardware by hand is error-prone and slow. This Skill automates the lowering of a high-level operator DSL into working AscendC host and kernel code, handling tiling, buffer management, data alignment, and multi-dtype support while automatically repairing compilation errors. ## Core Features & Use Cases - Multi-Pass Lowering Pipeline: Sequentially applies tiling_pass, kernel_config_pass, kernel_pass, entry_pass, and an optional multi_dtype_pass, compiling after each pass. - Automatic Error Recovery: Diagnoses compilation failures using curated error-correction references and retries up to three times per pass. - Hardware-Correct Patterns: Enforces dynamic core-count querying, pivot-based work distribution, DataCopyPad for non-aligned transfers, correct Cast modes for bfloat16, and pipeline barriers. - Use Case: Given a DSL file describing a LeakyRelu or matmul-style operator, generate a complete AscendC project (host tiling, op definition, kernel) that compiles for ascend910b and supports float32, float16, and bfloat16 variants. ## Quick Start Translate the operator DSL in output/my_op/my_op_dsl.py into AscendC code and compile each pass until the project builds successfully.
