dsp-algorithm

What problem does it solve?

This Skill eliminates the manual, error-prone work of designing, porting, and verifying DSP algorithms for ADSP-21569 SHARC+ DSPs used in directional column speakers, handling complex tasks like beamforming design, fixed-point conversion, and hardware accelerator integration that require deep domain expertise and strict compliance with project governance rules.

Core Features & Use Cases

• Beamforming Algorithm Design: Supports delay-sum (DSB), MVDR, GSC, subband MVDR, and Dolph-Chebyshev beamformer design with detailed implementation specifications and algorithm selection decision matrices.
• Fixed-Point Porting & Verification: Provides end-to-end Q format selection, overflow analysis, and bit-exact verification workflows to ensure floating-point algorithms are correctly ported to fixed-point SHARC+ targets with acceptable SNR loss.
• Hardware Integration & Performance Optimization: Covers FIRA hardware accelerator integration, SHARC compute budget (MIPS/MCPS) analysis, and latency optimization to meet real-time audio processing constraints for directional speaker systems.
• Use Case: An audio engineer developing a new directional column speaker can use this Skill to design a subband MVDR beamformer, port it to Q15 fixed-point format, verify bit-exact match with the floating-point reference, and optimize FIRA usage to stay within the ADSP-21569's MIPS and latency budgets.

Quick Start

Use the dsp-algorithm skill to design a Dolph-Chebyshev beamformer for an 8-element 100mm-spaced linear array, port it to Q15 fixed-point for the ADSP-21569 SHARC+, and generate a bit-exact verification report against the MATLAB floating-point reference.