dv-testplan

Generate a DV testplan Excel workbook from a design specification and parsed S1 data.

3|4|Updated Mar 21, 2026
One-click install
npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill dv-testplan
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: dv-testplan
Source: https://github.com/rajivhasija79-bit/DV-Skills/tree/main/skills/dv-testplan
Command: npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill dv-testplan

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Automates generation of a comprehensive DV testplan Excel workbook from a design spec or parsed S1 output. This enables DV teams to rapidly translate design intent into a structured verification plan, ensuring consistency across projects and speeding up downstream validation.

Core Features & Use Cases

  • Generate a structured Excel testplan with features, sub-features, test cases, coverage points, and checkers.
  • Auto-map registers and generate auto-test rows from a register map when provided in the S1 data.
  • Support directed, random (constrained and full) test generation, cross-coverage planning, and negative/edge-case tests.
  • Produce a Summary sheet with milestone coverage (DV-I, DV-C, DV-F) and a detailed Testplan sheet ready for Excel-based review and downstream automation.

Quick Start

Provide a SPEC_SOURCE (dv_spec_summary.json or raw spec) and PROJECT_NAME to begin, then run the dv-testplan workflow to generate testplan.xlsx.

Frequently Asked Questions about dv-testplan

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate a DV testplan Excel workbook from a design specification?

The workflow automates DV testplan generation by taking a design specification or parsed S1 output and a project name. It aggregates features, interfaces, and constraints to emit a structured Excel workbook for hardware verification.

Can I auto-generate register access test rows from a register map?

Yes, you can auto-generate register access test rows from a register map. When the parsed S1 data includes a register map, the workflow automatically maps the registers and creates corresponding test rows in the verification plan.

What types of verification and coverage planning are supported for hardware DV?

Hardware DV verification supports directed, constrained random, and full random test generation. It also handles cross-coverage planning, negative tests, and edge-case tests to ensure comprehensive design validation across various clock domains.

Does the generated testplan include milestone coverage tracking?

Yes, the generated testplan includes milestone coverage tracking. It produces a Summary sheet with milestone coverage phases like DV-I, DV-C, and DV-F, alongside a detailed Testplan sheet for downstream validation tracking.

What input formats do I need to start automated verification planning?

You need a SPEC_SOURCE, such as a dv_spec_summary.json file or a raw design spec, and a PROJECT_NAME to begin. These inputs allow the workflow to parse design intent and output the structured verification plan.