Agent Skills by rajivhasija79-bit
Showing 14 vetted skills indexed across 1 GitHub repositories.
rajivhasija79-bitrtl-sim-debug-pcie-dummy
Diagnose PCIe RTL debug failures with domain-specific context for controller, PIPE PHY, LTSSM, TLP, DLLP, and flow-control.
rajivhasija79-bitskill-creator
Draft, test, and evaluate Claude skills through iterative refinement.
rajivhasija79-bitrtl-sim-debug
Triage RTL/VCS failures via log analysis, waveform inspection, and JIRA correlation.
rajivhasija79-bitdv-spec-parse
Parse hardware design specifications into structured DV spec JSON and summaries.
rajivhasija79-bitdv-scoreboard
Generate DV scoreboard, reference model, and coverage wiring from JSON and testplan data.
rajivhasija79-bitdv-regression
Generate DV regression test lists, configure grid runs, and produce HTML reports.
rajivhasija79-bitdv-sequences
Generate UVM sequences, virtual sequences, and test classes from a DV testplan.
rajivhasija79-bitdv-verif-plan
Generate a DV verification plan PDF and JSON payload from S1 spec and S2 testplan.
rajivhasija79-bitdv-testplan
Generate a DV testplan Excel workbook from a design specification and parsed S1 data.
rajivhasija79-bitS10 — DV Coverage Closure
Analyze URG reports to classify DV coverage gaps and generate exclusion files.
rajivhasija79-bitdv-env-setup
Generate a complete DV environment scaffold with directory structure, Makefiles, and UVM skeletons.
rajivhasija79-bitpptx
Read, edit, and generate PPTX slides with XML validation.
rajivhasija79-bitdv-tb-scaffold
Generate a complete UVM DV testbench scaffold from a DUT specification.
rajivhasija79-bitdv-assertions
Generate SystemVerilog Assertions from testplans and TB data for DV environments.