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ESP32-S3 PIE SIMD Optimization

Converts scalar C loops into ESP32-S3 PIE SIMD assembly using EE.* instructions.

1.1k|222|Updated Nov 16, 2018
Search Tags:#embedded#Optimization#simd#assembly#xtensa#esp32-s3#pie
One-click install
npx skills add https://github.com/espressif/esp-dl --skill esp32-s3-pie-simd-optimization
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: ESP32-S3 PIE SIMD Optimization
Source: https://github.com/espressif/esp-dl/tree/main/tools/agents/skills/esp32s3-pie-simd
Command: npx skills add https://github.com/espressif/esp-dl --skill esp32-s3-pie-simd-optimization

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Writing SIMD assembly for the ESP32-S3's Processor Instruction Extensions (PIE) is error-prone: developers must manage 128-bit QR registers, forced memory alignment, SAR shift configuration, and accumulator semantics. This Skill provides a complete reference and conversion patterns to translate scalar C loops into correct, optimized PIE assembly.

Core Features & Use Cases

  • Instruction Reference: Covers all EE.* instruction classes including vector arithmetic, multiply-accumulate (ACCX/QACC), comparison, bitwise, FFT, and unaligned load handling.
  • C-to-SIMD Conversion Patterns: Provides ready-made templates for element-wise arithmetic, dot products, ReLU/PReLU activations, bias addition, and max pooling.
  • Constraint Guidance: Documents alignment rules, register pressure limits (only q0-q7), zero-overhead loop constraints, and pipeline scheduling pitfalls.
  • Use Case: When optimizing a quantized neural network kernel on ESP32-S3, use this Skill to rewrite an int16 dot-product loop with EE.VMULAS.S16.ACCX and correct accumulator extraction.

Quick Start

Ask the agent to convert a scalar C loop, such as an int16 element-wise add or dot product, into ESP32-S3 PIE SIMD assembly using this skill.

Frequently Asked Questions about ESP32-S3 PIE SIMD Optimization

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I convert a C loop to ESP32-S3 PIE SIMD assembly?▼

Identify the operation and data type, ensure buffers are 16-byte aligned, select the matching EE.* instruction from the decision table, set SAR if multiplying, and wrap the body in a loopgtz zero-overhead loop with iteration count N divided by lanes per register.

What is the difference between ACCX and QACC accumulators on ESP32-S3?▼

ACCX is a single 40-bit scalar accumulator summing all lane products, ideal for dot products. QACC provides per-lane accumulation with 16 lanes of 20-bit (8-bit data) or 8 lanes of 40-bit (16-bit data), suited for per-channel results like quantized convolution.

How do I handle unaligned data with PIE load instructions?▼

Use the three-instruction pattern: EE.LD.128.USAR.IP loads the aligned chunk and saves the offset to SAR_BYTE, EE.VLD.128.IP loads the next chunk, then EE.SRC.Q shifts and concatenates the pair to recover the unaligned vector.

Why does my PIE SIMD code read wrong data at some addresses?▼

PIE loads and stores force address low bits to zero, so unaligned addresses silently access the wrong location. Declare buffers with __attribute__((aligned(16))) or allocate with heap_caps_aligned_alloc(16, size, MALLOC_CAP_DEFAULT).

What are the limitations of PIE SIMD on ESP32-S3?▼

Only 8 QR registers (q0-q7) are available, there is no 32-bit vector multiply, zero-overhead loops are limited to roughly 56 instructions with no nesting, and VMUL truncates after shifting without saturation.

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