flydsl-kernel-authoring

To write a custom GPU kernel for AMD MI300X, use FlyDSL's explicit layout algebra and MLIR-backed compiler pipeline to construct tiled kernels, manage data movement, and integrate MFMA operations for gfx942/gfx950 architectures.

Layout algebra in AMDGPU kernels defines explicit memory access patterns and tiling strategies for data movement. It allows developers to structure kernel construction using MLIR, optimizing buffer operations and scf.for loops for MI300X and MI350 GPUs.

Yes, developing FlyDSL kernels on ROCm requires familiarity with Python and MLIR. End-to-end kernel development also expects knowledge of ROCm tooling to effectively handle layout construction, memory access patterns, and optional autotuning workflows.

Yes, you can implement GEMM and vector operations on MI350 GPUs using FlyDSL. The framework provides practical patterns and recipes for element-wise kernels, data movement, and explicit layouts tailored for AMD gfx942/gfx950 architectures.

To optimize memory access patterns and buffer ops in AMDGPU kernels, utilize FlyDSL's SmemAllocator and tiled copy operations. These tools help manage data movement and memory layout construction effectively within the MLIR compiler pipeline.

The best way to autotune AMDGPU kernels written with FlyDSL is to use the provided autotuning workflows. These workflows integrate with the MLIR-backed compiler pipeline to optimize tiled copy and MMA operations across different explicit layouts for MI300X/MI350 GPUs.