Generate RTL implementation plans for SystemVerilog hardware designs.
npx skills add https://github.com/RedClaus/cortex --skill gf-plan-redclaus
Please help me install this Agent Skill. Skill: gf-plan Source: https://github.com/RedClaus/cortex/tree/main/core/plugins/gateflow/skills/gf-plan Command: npx skills add https://github.com/RedClaus/cortex --skill gf-plan-redclaus
This Skill automates the creation of comprehensive RTL implementation plans for hardware designs, ensuring all critical aspects are considered before coding begins.
Use the gf-plan skill to generate a detailed RTL implementation plan for a new DMA controller.
High-intent search queries and answers about installing and using this skill.
To generate an RTL implementation plan for SystemVerilog hardware design, you need to define the architecture, interfaces, clocking strategies, resets, FSMs, pipelines, and verification test cases before coding begins.
A comprehensive hardware design planning document should include block diagrams, interface specifications, clocking strategies, reset domains, FSM definitions, pipeline structures, and a detailed verification strategy.
Yes, you can use this for planning complex components like a DMA controller architecture. It generates a complete RTL implementation plan covering everything from block-level architecture to verification test cases.
To structure the verification strategy during RTL planning, you must define verification approaches and test cases alongside the hardware architecture, ensuring all critical aspects are considered before SystemVerilog coding begins.
Yes, this supports phased hardware design planning from requirements to verification. It guides users through a structured workflow process to ensure all critical hardware components are specified.
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