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rtl-security-review

Review Verilog, SystemVerilog, and VHDL RTL designs for security vulnerabilities.

1|1|Updated Feb 21, 2026
Search Tags:#security#vulnerability analysis#rtl#verilog#hardware design#vhdl
One-click install
npx skills add https://github.com/dtsong/claude-code-windows-setup --skill rtl-security-review
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-security-review
Source: https://github.com/dtsong/claude-code-windows-setup/tree/main/skills/council/forge/rtl-security-review
Command: npx skills add https://github.com/dtsong/claude-code-windows-setup --skill rtl-security-review

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill identifies and mitigates security vulnerabilities within Register Transfer Level (RTL) designs, ensuring hardware integrity and preventing exploits.

Core Features & Use Cases

  • Vulnerability Detection: Analyzes Verilog, SystemVerilog, and VHDL for access control bypasses, insecure FSM transitions, timing leaks, and unintended data paths.
  • Policy Enforcement: Verifies adherence to security policies and trust boundary definitions.
  • Use Case: A hardware security engineer can use this skill to perform a thorough security audit on a new cryptographic module's RTL code before tape-out, identifying critical flaws like a bypassable access control gate.

Quick Start

Review the attached Verilog file 'secure_module.v' for security vulnerabilities.

Frequently Asked Questions about rtl-security-review

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I review Verilog and VHDL modules for security vulnerabilities?▼

Reviewing Verilog and VHDL modules for security vulnerabilities involves analyzing RTL source against security policies and trust boundaries to detect access control bypasses, insecure FSM transitions, and timing leaks.

What types of hardware security flaws can RTL analysis detect?▼

RTL analysis detects hardware security flaws including access control gate bypasses, insecure FSM transitions, timing-dependent information leakage, and unintended data paths within security-critical functions.

What do I need to provide for an RTL security audit?▼

For an RTL security audit, you need to provide RTL source files, security policy specifications, trust boundary definitions, and intended FSM behavior to ensure comprehensive vulnerability detection.

Can I check SystemVerilog designs for timing-dependent information leakage?▼

Yes, you can check SystemVerilog designs for timing-dependent information leakage by analyzing the RTL source code against defined security policies to identify and mitigate critical timing flaws.

How do I verify access control gates in SystemVerilog before tape-out?▼

Verify access control gates in SystemVerilog before tape-out by reviewing the RTL designs against security policy specifications and trust boundary definitions to identify and mitigate bypass vulnerabilities.

When do I need to define trust boundaries for VHDL vulnerability analysis?▼

You need to define trust boundaries for VHDL vulnerability analysis whenever evaluating security-critical functions to ensure the review accurately detects unintended data paths and access control bypasses.

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