test-design-policy

RTL test cases are derived from microarchitecture specifications by applying equivalence partitioning, boundary value analysis, state transition, and decision table techniques to generate a coverage-mapped test vector set.

Boundary value analysis for RTL verification enumerates boundary and corner values for signed and unsigned integers, addresses, and counters to catch off-by-one and overflow conditions in test vectors.

FSM state transitions for RTL test planning are extracted from microarchitecture specifications to ensure mandatory transition coverage and build decision tables for multi-boolean control logic.

Equivalence partitioning applies to both datapath and control module verification by identifying valid and invalid input classes to select representative values for input domains across different module types.

An io definition and uarch spec are required to generate a coverage-driven test plan, as they provide the necessary input domains, state machines, and control logic for systematic test vector derivation.

Ad-hoc RTL test generation fails to achieve measurable coverage goals because it lacks systematic techniques like equivalence partitioning and boundary value analysis, resulting in incomplete vector sets for verification planning.