Apply loop unroll and N-slice tiling to reduce GPR pressure in Gluon GEMM kernels.
npx skills add https://github.com/leonling-ll/claude-skills --skill gluon-gpr-opt
Please help me install this Agent Skill. Skill: gluon-gpr-opt Source: https://github.com/leonling-ll/claude-skills/tree/main/gluon-gpr-opt Command: npx skills add https://github.com/leonling-ll/claude-skills --skill gluon-gpr-opt
General-purpose registers (GPRs) pressure and LDS- and MFMA-bound stalls limit performance of Gluon GEMM kernels on CDNA3 and CDNA4 GPUs. This skill provides a structured approach to reduce GPR pressure and improve pipeline overlap by applying a two-stage optimization: Stage 1 loop unroll ×2 to eliminate k%2 modulo overhead, and Stage 2 N-slice tiling to split the B tile into left/right halves, enabling concurrent data movement and computation across gfx942/MI300X/MI308X/MI325X (CDNA3) and gfx950/MI350 (CDNA4).
Apply Stage 1 loop unroll ×2 first; if residual bubbles remain, enable Stage 2 N-slice tiling and validate improvements.
High-intent search queries and answers about installing and using this skill.
To reduce GPR pressure in Gluon GEMM kernels on CDNA3 GPUs, apply Stage 1 loop unroll ×2 to eliminate k%2 modulo overhead and statically resolve LDS slot accesses, then apply Stage 2 N-slice tiling to hide DMA loads behind MFMA operations.
N-slice tiling accelerates MFMA operations on CDNA4 by splitting the B tile into left and right halves, enabling concurrent data movement and computation to reduce pipeline bubbles and hide latency in large BLOCK_N configurations.
Yes, the Gluon GEMM GPR optimization works with both MI300X and MI350 GPUs, utilizing architecture-specific primitives like buffer_load and ds_write on CDNA3, and async_copy and commit_group on CDNA4.
To eliminate k%2 modulo overhead in Gluon GEMM, apply Stage 1 loop unroll ×2 by hardcoding g_idx and l_idx, which enables the compiler to resolve LDS slot accesses statically without dynamic modulo calculations.
N-slice tiling and double-buffered LDS with local prefetch require K to be constexpr in Gluon GEMM kernels to ensure static resolution of loop iterations and enable the compiler to apply Stage 1 loop unroll ×2 effectively.
Limitations of loop unroll and N-slice tiling for GPR optimization include requiring K to be constexpr, targeting only CDNA3/CDNA4 architectures, and needing validation of residual pipeline bubbles after Stage 1 before enabling Stage 2.
leonling-llImplement two-stage pipeline optimizations for Gluon GEMM kernels on CDNA3 and CDNA4 GPUs.
leonling-llApply XCD remapping and epilogue slicing to Gluon GEMM kernels.
leonling-llReplace global memory loads with AMD-native buffer instructions in Gluon GEMM kernels.
leonling-llOptimizes Gluon GEMM kernel layouts to eliminate LDS bank conflicts on Coprocessor Design's NEXT-GEN GPUs.
