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hardware-audit

Audit ESP32 PCB designs for electrical and manufacturing defects.

2|Updated Feb 8, 2026
Search Tags:#design-intent#pcb#kicad#dfm#hardware-audit#esp32-s3#power-audit
One-click install
npx skills add https://github.com/pjcau/esp32-emu-turbo --skill hardware-audit
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: hardware-audit
Source: https://github.com/pjcau/esp32-emu-turbo/tree/main/.claude/skills/hardware-audit
Command: npx skills add https://github.com/pjcau/esp32-emu-turbo --skill hardware-audit

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Provides a two-layer electrical and functional audit for the ESP32 Emu Turbo hardware design, combining deterministic automated geometry, DFM, and connectivity gates with a manual domain-by-domain review to find issues that would prevent board power-on, component operation, or emulator functionality.

Core Features & Use Cases

  • Layer 1 Automated Gates: Run an exhaustive script suite to detect trace-through-pad overlaps, same-layer trace crossings, copper-clearance DANGER zones, per-net connectivity fragmentation, DFM/DFA violations, datasheet pin→net mismatches, and power-path integrity issues.
  • Layer 2 Manual Review: Guided prose audits across power chain, ESP32 boot strapping, display wiring, audio path, SD card routing, buttons, USB, and emulator performance expectations.
  • Deterministic Halt & Reporting: If any Layer 1 gate fails, the workflow stops and writes a structured finding into hardware-audit-bugs.md; otherwise the auditor proceeds to documented manual checks with severity-tagged bug entries.
  • Use Case: Pre-fabrication validation of an ESP32-S3 handheld console PCB to catch manufacturing and functional regressions before ordering panels or populating assemblies.

Quick Start

Run the Layer 1 automated gate suite, then perform the Layer 2 domain-by-domain review and save findings to hardware-audit-bugs.md.

Frequently Asked Questions about hardware-audit

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I run a pre-fabrication PCB hardware audit to catch electrical defects?▼

Run automated geometric DRC and DFM gates to detect trace overlaps and clearance violations, then execute manual domain reviews for power, boot strapping, and signal integrity to validate the PCB before fabrication.

What electrical and manufacturing issues does a KiCad DFM and connectivity audit detect?▼

A DFM and connectivity audit detects trace-through-pad overlaps, same-layer trace crossings, copper-clearance DANGER zones, per-net connectivity fragmentation, and datasheet pin-to-net mismatches that prevent proper board power-on and component operation.

Can I validate ESP32-S3 boot strapping and power integrity before ordering PCB assemblies?▼

Yes, you can validate ESP32-S3 boot strapping and power integrity by applying per-net connectivity checks, power-path validations, and manual domain reviews to ensure the hardware design functions correctly before ordering populated assemblies.

How do I check ESP32 datasheet pin-to-net mismatches during board validation?▼

Check ESP32 datasheet pin-to-net mismatches by executing deterministic automated connectivity gates that compare PCB net assignments against datasheet pinouts, halting the validation workflow and logging structured bugs when any mismatch occurs.

What is the best way to report PCB design-intent and DFM violations found during validation?▼

Report PCB design-intent and DFM violations by writing structured, severity-tagged findings into a hardware-audit-bugs.md file, automatically halting the audit workflow when any Layer 1 automated gate fails to ensure defects are documented.

Does automated PCB DRC replace manual signal integrity and boot strapping reviews?▼

Automated PCB DRC does not replace manual reviews; a complete hardware audit requires Layer 2 guided prose audits across the power chain, ESP32 boot strapping, display wiring, audio path, and SD card routing to find functional regressions.

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