hil-harness

Enforce four-rung verification ladders for safety-critical embedded functions.

3|2|Updated Jan 23, 2026
One-click install
npx skills add https://github.com/robotijn/ctoc --skill hil-harness
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: hil-harness
Source: https://github.com/robotijn/ctoc/tree/main/skills/realtime/hil-harness
Command: npx skills add https://github.com/robotijn/ctoc --skill hil-harness

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Safety-critical embedded systems risk shipping undetected defects when verification rungs of the V-model are skipped without documentation, leading to costly recalls or regulatory non-compliance for automotive, aerospace, and industrial safety applications.

Core Features & Use Cases

  • Four-Rung Verification Ladder: Automatically maps each safety-relevant function to the appropriate Model-in-the-Loop, Software-in-the-Loop, Processor-in-the-Loop, or Hardware-in-the-Loop test rung based on active regulatory requirements (ISO 26262, DO-178C, IEC 61508).
  • Gap Documentation Enforcement: Treats all missing or skipped rungs as documented assurance gaps with required written rationales, eliminating silent verification oversights.
  • Fault Injection Alignment: Derives Hardware-in-the-Loop fault-injection scenarios directly from Failure Modes Effects and Diagnostic Analysis (FMEDA) to cover all dangerous failure modes. Use Case: For an ASIL-D automotive emergency brake function, this skill ensures MIL tests validate the control model against requirements, SIL tests catch code generation mismatches, PIL tests verify target compiler behavior, and HIL tests exercise real-time timing and fault response on the physical ECU rig.

Quick Start

Use the hil-harness skill to generate a complete verification ladder report for the current embedded safety-critical plan, including per-rung evidence status and all missing gap findings.

Frequently Asked Questions about hil-harness

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
What is the V-model verification ladder for safety-critical embedded systems?

Hardware-in-the-Loop testing validates real-time timing and physical fault responses on the target ECU rig. It is required to satisfy regulatory fault injection coverage and Worst-Case Execution Time corroboration for safety-critical embedded systems.

How do I align fault injection scenarios with FMEDA for ISO 26262 compliance?

You handle skipped verification rungs by treating them as documented assurance gaps with required written rationales. This enforces gap documentation to prevent silent verification oversights and satisfy regulatory evidence requirements.

Can I use this to verify ASIL-D automotive emergency brake functions on a physical ECU rig?

Yes, you can verify ASIL-D brake functions by enforcing the complete MIL to HIL verification ladder. This ensures model validation, code generation mismatch detection, compiler behavior verification, and physical ECU real-time fault response testing.

How to generate machine-readable HIL ladder artifacts for DO-178C regulatory evidence?

Generate machine-readable HIL ladder artifacts by mapping each safety-relevant function to its minimum required verification rung. The process flags missing, stale, or contradictory verification evidence to satisfy DO-178C regulatory test evidence requirements.