kernel-tileir-optimization

To optimize Triton kernel performance on Blackwell GPUs, apply TileIR-specific autotune configurations for occupancy, num_ctas, and num_stages, then validate correctness using ENABLE_TILE compatibility mode toggling.

TileIR autotune strategy selects backend-specific configurations for Triton kernels by classifying them as dot-related, norm-like, element-wise, or reduction, then applying appropriate occupancy, num_stages, and TMA/2CTA wiring parameters.

TMA descriptors for dot-related Triton kernels require specific wiring patterns including pre-hook updates to avoid runtime errors or silent wrong results, using 2CTA configurations within the TileIR autotune strategy on Blackwell GPUs.

No, TileIR optimization applies to existing Triton kernels by changing autotune configurations rather than rewriting kernel logic, targeting dot-related, norm-like, element-wise, and reduction kernels that need TileIR parameter updates.

Validate Triton kernel correctness by running with ENABLE_TILE=0 in compatibility mode to compare standard PTX output against TileIR performance, ensuring the optimized autotune configurations produce accurate results.

TileIR optimization supports dot-related, norm-like, element-wise, and reduction kernels on Blackwell GPUs, but requires ENABLE_TILE gating and specific TMA/2CTA wiring for dot kernels, making it unsuitable for kernels needing logic rewrites.