prefetch-data-load

You can overlap GPU memory latency with compute in FlyDSL by introducing loop-carried prefetch patterns using scf.for with init values to issue async buffer_load operations for the next iteration while processing MFMA compute on current data.

Loop-carried prefetch with scf.for works by preloading first iteration data, issuing async next-iteration loads inside the loop, and swapping raw MLIR ir.Value buffers at the loop tail to hide memory latency behind compute.

Yes, prefetch data load patterns apply specifically to FlyDSL kernels where buffer_load results feed into MFMA or compute operations, allowing next-iteration loads to be issued asynchronously and swapped into current data.

Managing VGPR budget when implementing data prefetch requires mindful planning of loop-carried init values in scf.for to avoid register spills, as carrying prefetched buffer_load data across iterations increases register pressure.

Unwrapping values to raw MLIR ir.Value is required for prefetching in FlyDSL because the loop-carried scf.for init values must be swapped at the loop tail to properly exchange current and next-iteration async load buffers.