Optimizes GEMM kernels on AMD CDNA GPUs using FlyDSL tiling, memory layout, MFMA scheduling.
npx skills add https://github.com/ROCm/FlyDSL --skill gemm-optimization
Please help me install this Agent Skill. Skill: gemm-optimization Source: https://github.com/ROCm/FlyDSL/tree/main/.claude/skills/gemm-optimization Command: npx skills add https://github.com/ROCm/FlyDSL --skill gemm-optimization
FlyDSL GEMM optimization provides a comprehensive guide to maximizing performance of GEMM kernels on AMD CDNA GPUs by detailing tiling strategies, memory layouts, and MFMA scheduling patterns.
Follow the guide to implement GEMM optimizations for an AMD CDNA GPU using FlyDSL, starting with selecting tile_m, tile_n, and tile_k and enabling 2-stage LDS where appropriate.
High-intent search queries and answers about installing and using this skill.
Optimize GEMM kernels on AMD CDNA by selecting tile_m, tile_n, and tile_k sizes, enabling 2-stage LDS double buffering, and configuring MFMA scheduling patterns using FlyDSL to maximize hardware utilization.
Resolve LDS bank conflicts during GEMM tiling by applying XOR bank-conflict mitigation techniques alongside LDS ping-pong double buffering to ensure smooth memory access and improve bandwidth.
Compare Direct Store versus CShuffle for GEMM epilogue based on specific memory layout requirements; evaluate both strategies using ATT trace bottleneck diagnosis to determine the optimal bandwidth configuration.
Two-stage software pipelining improves MFMA scheduling by overlapping memory loads with computations using A/B prefetch pipelines and a hot_loop_scheduler, maximizing TFLOPS and ensuring continuous matrix instruction throughput.
Profile ATT traces to diagnose GEMM kernel bottlenecks by evaluating LDS bandwidth, MFMA utilization, and identifying specific memory or compute stalls, enabling iterative kernel optimization on AMD CDNA.
FlyDSL supports CDNA architectures by providing comprehensive tiling strategies and memory layout configurations tailored for MFMA scheduling, satisfying specific requirements for hardware utilization and bandwidth.
ROCmGenerate and validate FlyDSL GPU kernels from kernel specifications using tile programming.
leonling-llCollect timing, hardware counters, ATT traces, and memory-hierarchy data from AMD GPU kernels.
leonling-llOptimizes Gluon GEMM kernel layouts to eliminate LDS bank conflicts on Coprocessor Design's NEXT-GEN GPUs.
leonling-llTranslate Triton GPU kernels to explicit AMD Gluon kernels for CDNA GPUs.
