Translate Triton GPU kernels to explicit AMD Gluon kernels for CDNA GPUs.
npx skills add https://github.com/leonling-ll/claude-skills --skill triton-to-gluon
Please help me install this Agent Skill. Skill: triton-to-gluon Source: https://github.com/leonling-ll/claude-skills/tree/main/triton-to-gluon Command: npx skills add https://github.com/leonling-ll/claude-skills --skill triton-to-gluon
Translate a Triton GPU kernel into an explicit Gluon kernel that uses AMD tensor layouts to enable efficient execution on CDNA GPUs.
Run the translation on your Triton kernel file, for example /triton-to-gluon <kernel_file.py>.
High-intent search queries and answers about installing and using this skill.
To translate Triton kernels to Gluon for AMD CDNA GPUs, you run the translation on your kernel file. The tool extracts TTGIR/LLIR artifacts, detects the GPU architecture, generates explicit layouts, and saves the ported Gluon kernel artifacts.
Porting Triton to Gluon supports AMD CDNA GPUs, specifically detecting gfx942 for CDNA3 and gfx950 for CDNA4 architectures. This covers porting workflows for MI300X, MI308X, and MI350 hardware to ensure proper layout conventions.
Translating Triton to Gluon generates explicit tensor layouts including BlockedLayout, SwizzledSharedLayout, AMDMFMALayout, and DotOperandLayout. These layouts are derived by dumping Triton IR artifacts to enable efficient execution on AMD GPUs.
Porting Triton kernels to AMD Gluon includes an integrated verify and profiler workflow. It uses torch.profiler to ensure correctness and extract precise tensor layouts and pipeline structure during the translation process.
Extracting TTGIR and LLIR artifacts is required to derive precise tensor layouts and pipeline structure when porting Triton kernels to AMD GPUs. This explicit layout generation ensures the Gluon kernel executes efficiently on CDNA hardware.
You can port matmul, attention, and linear kernels from Triton to Gluon on AMD GPUs. The translation process integrates with existing porting workflows to generate explicit AMD tensor layouts for these specific kernel types.
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