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rtl-property-inference

Infer formal correctness properties from Verilog/SystemVerilog RTL and generate SVA assertions.

142|14|Updated Feb 14, 2026
Search Tags:#verification#rtl#hardware design#sva#assertion generation#formal properties
One-click install
npx skills add https://github.com/ArabelaTso/Skills-4-SE --skill rtl-property-inference
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-property-inference
Source: https://github.com/ArabelaTso/Skills-4-SE/tree/main/skills/rtl-property-inference
Command: npx skills add https://github.com/ArabelaTso/Skills-4-SE --skill rtl-property-inference

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill automates the generation of formal correctness properties (SystemVerilog Assertions - SVA) directly from Verilog/SystemVerilog RTL code, reducing manual effort and improving hardware verification.

Core Features & Use Cases

  • Automated Property Inference: Identifies common hardware design patterns (handshakes, state machines, pipelines) and infers relevant safety, liveness, and fairness properties.
  • SVA Generation: Outputs well-formed SVA code with natural-language explanations for each inferred property.
  • Use Case: When integrating a new RTL module, use this Skill to automatically generate assertions that capture its intended behavior, ensuring it adheres to expected protocols and invariants.

Quick Start

Use the rtl-property-inference skill to infer properties from the provided Verilog file 'my_module.v'.

Frequently Asked Questions about rtl-property-inference

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automatically generate SystemVerilog Assertions from existing RTL code?▼

Automated SVA generation analyzes Verilog or SystemVerilog RTL to identify control-flow invariants, liveness expectations, and temporal properties. It recognizes structural patterns like state machines and handshakes to map them to assertion templates.

What types of formal properties can be inferred from hardware design patterns?▼

Formal property inference identifies safety, liveness, and fairness properties from common hardware patterns. It detects state machines, handshakes, and pipelines to infer relevant control-flow invariants and temporal properties.

Can I infer formal correctness properties for new Verilog modules without writing assertions manually?▼

Yes, you can infer formal correctness properties for new Verilog modules by parsing RTL code to extract signals and map common hardware patterns to SVA templates. This reduces manual effort and ensures modules adhere to expected protocols.

How does automated assertion generation handle temporal properties and liveness expectations in SystemVerilog?▼

Automated assertion generation handles temporal properties by analyzing design structure and mapping recognized hardware patterns to SVA templates. It outputs well-formed SystemVerilog Assertions with natural-language explanations for each inferred liveness expectation.

What are the limitations of automated SVA property inference for complex state machines?▼

Automated SVA inference relies on recognizing common hardware design patterns, meaning highly custom or unconventional state machine logic may not map cleanly to standard SVA templates. Complex control-flow invariants require structural pattern recognition to succeed.

Does the rtl-property-inference skill provide natural-language explanations for the SVA it generates?▼

Yes, the rtl-property-inference skill outputs well-formed SVA code alongside natural-language explanations for each inferred property. This clarifies the identified safety, liveness, and temporal properties mapped from the hardware design.

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