Diagnose DW3000 SPI communication failures on STM32 HAL.
npx skills add https://github.com/51hhh/BU03 --skill stm32-dw3000-spi
Please help me install this Agent Skill. Skill: stm32-dw3000-spi Source: https://github.com/51hhh/BU03/tree/main/.github/skills/stm32-dw3000-spi Command: npx skills add https://github.com/51hhh/BU03 --skill stm32-dw3000-spi
This Skill helps diagnose and fix DW3000 SPI communication failures on STM32, especially cases where device ID reads fail, chip select timing is wrong, or the radio does not respond during bring-up.
Use this skill to analyze a DW3000 SPI read failure on STM32 and identify the most likely cause from the observed DEV_ID value and transfer behavior.
High-intent search queries and answers about installing and using this skill.
Failed DW3000 SPI reads on STM32 typically indicate incorrect SPI mode 0 configuration, chip-select timing violations, or missing mutex protection around SPI access. Diagnosing DEV_ID read failures requires verifying full-duplex transfers and staged clock rates.
To configure STM32 HAL SPI for DW3000 reads, use single-call full-duplex transfers, ensure strict chip-select hold timing, and apply SPI mode 0. Staged SPI clock rates during initialization prevent communication errors when reading DEV_ID.
Random DW3000 DEV_ID reads often stem from interrupt contention, incorrect SPI mode, or unstable chip-select timing. Analyzing EAMRW-related transfer issues and applying mutex protection around SPI access isolates the driver or wiring fault.
Yes, mutex protection around SPI access is required for DW3000 transfers on STM32. It prevents interrupt contention and ensures strict chip-select hold timing during single-call full-duplex transfers, avoiding corrupted EAMRW data.
DW3000 initialization on STM32 requires staged SPI clock rates, starting slow before increasing speed. This ensures reliable chip-select timing and full-duplex transfer stability during the critical DEV_ID read phase of bring-up.
Standard STM32 HAL SPI functions work for DW3000 EAMRW transfers if configured for single-call full-duplex mode with strict chip-select hold timing. Proper SPI mode 0 and mutex protection must be maintained to prevent data corruption.
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