tilelang

Develop Python GPU kernels with explicit shared memory and warp-level control.

1|Updated Jun 4, 2026
One-click install
npx skills add https://github.com/hung-phan/ml-skills --skill tilelang-hung-phan
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: tilelang
Source: https://github.com/hung-phan/ml-skills/tree/main/skills/ml-review/references/gpu-lang/tilelang
Command: npx skills add https://github.com/hung-phan/ml-skills --skill tilelang-hung-phan

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires tvm, tvm-tir, and includes scripts (resource) and references (resource) components.

What problem does it solve?

TileLang addresses the gap in GPU kernel development tooling by providing explicit control over shared memory, warp-level operations, and pipeline staging, compiling to CUDA/HIP via TVM/TIR.

Core Features & Use Cases

  • Explicit Shared Memory Management: Control over shared memory at each level for optimal performance.
  • Warp-Level Primitives: Fine-grained control over warps for efficient computation.
  • Multi-Stage Software Pipelining: Explicit pipeline depth for latency hiding.
  • Compilation via TVM/TIR: Lower through TVM's Tensor IR for CUDA/HIP/WebGPU/CPU.
  • Use Case: Develop complex GPU kernels for tasks like FlashAttention, MLA, and convolutions with Pythonic DSL code.

Quick Start

Install TileLang and write your first kernel to perform a GEMM operation.

Frequently Asked Questions about tilelang

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write high-performance GPU kernels in Python with shared memory and warp control?

Write high-performance GPU kernels in Python using a DSL that provides explicit control over shared memory, warp-level operations, and pipeline staging. Code is lowered to CUDA or HIP via TVM Tensor IR for optimized hardware execution.

Does TVM TIR support compiling Python GPU kernels to CUDA and HIP?

Yes, TVM TIR supports compiling Python GPU kernels to CUDA, HIP, WebGPU, and CPU. This lowering process translates high-level Pythonic DSL code into optimized hardware-specific instructions.

What is the best way to implement multi-stage software pipelining for GPU computations?

Implement multi-stage software pipelining for GPU computations by explicitly defining pipeline depth in a Pythonic DSL. This approach hides memory latency and optimizes complex tasks like FlashAttention and convolutions.

Can I optimize FlashAttention and MLA computations using a Pythonic DSL?

Yes, you can optimize FlashAttention and MLA computations using a Pythonic DSL. It allows fine-grained management of shared memory and warp-level primitives to achieve high performance on complex GPU operations.

Do I need TVM to compile TileLang GPU kernels?

Yes, TVM is required as a dependency. The framework lowers Python GPU kernels through TVM's Tensor IR to generate executable code for CUDA, HIP, WebGPU, and CPU backends.

Why use a Python DSL for GPU programming instead of writing raw CUDA?

Use a Python DSL for GPU programming to gain fine-grained control over shared memory and pipeline staging while avoiding complex low-level CUDA syntax. It lowers through TVM TIR to achieve comparable hardware performance.