万众一芯开放验证 (UnityChip Verification)
Official@xs-mlvp
Open-source tools, examples in chip verification
Agent Skills by 万众一芯开放验证 (UnityChip Verification)
Showing 13 vetted skills indexed across 1 GitHub repositories.
XS-MLVPucagent
Automate multi-step task workflows via YAML-configured missions and stages.
XS-MLVPsva-audit
Automate SVA environment analysis by filling formal records from verification results.
XS-MLVPcex-gen
Generate Python test function scaffolds for RTL bugs from wrapper.sv.
XS-MLVPsva-gen
Convert YAML SVA bodies into SystemVerilog assertions for formal checks.
XS-MLVPfunc-spec
Extract DUT functional specifications into hierarchical YAML records via update_spec.py.
XS-MLVPbug-report
Scaffold RTL_BUG entries from verification analysis into .formal_records.yaml.
XS-MLVPsva-opt
Analyze COI coverage data and generate SVA assertions for uncovered signals.
XS-MLVPstatic-bug-analysis
Analyze RTL designs for static bugs using FG/FC/CK taxonomy.
XS-MLVPstatic-bug-validation
Validate and link static bug analysis placeholders to dynamic bug records.
XS-MLVPtest-case-implementation-in-batch
Automate batch test-case implementation and structured bug analysis workflows.
XS-MLVPcreate-test-case-templates
Generate standardized test-case templates from Markdown definitions and reference files using Python scripts.
XS-MLVPfunctions-and-checks
Structure DUT functionality into FG/FC/CK hierarchies for test design documentation.
XS-MLVPucagent-client
Control a UCAgent CMD API server over Unix sockets or HTTP(S).
Frequently Asked Questions About 万众一芯开放验证 (UnityChip Verification)
FAQPage SchemaWhat specific verification tasks does UnityChip enable?▼
UnityChip enables the extraction of DUT functional specifications into YAML, the generation of SystemVerilog assertions from formal records, and the systematic analysis of RTL designs for static bugs using FG/FC/CK taxonomy. It streamlines the transition from design documentation to formal verification environments.
Which engineering personas benefit from these verification capabilities?▼
Verification engineers, RTL designers, and formal verification specialists benefit from these capabilities. The platform is designed for professionals managing complex chip verification cycles who require structured, repeatable methods for assertion generation and bug tracking across large-scale hardware design projects.
What are the prerequisites for deploying UnityChip verification components?▼
Deployment requires a Unix-based environment capable of executing YAML-configured missions and processing SystemVerilog files. Users must maintain a structured DUT functional specification in YAML format and have access to standard RTL design files to facilitate the generation of assertion scaffolds and bug analysis records.