sva-gen

Convert YAML SVA bodies into SystemVerilog assertions for formal checks.

207|45|Updated May 27, 2025
One-click install
npx skills add https://github.com/XS-MLVP/UCAgent --skill sva-gen
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: sva-gen
Source: https://github.com/XS-MLVP/UCAgent/tree/main/ucagent/lang/zh/skills/formal/sva-gen
Command: npx skills add https://github.com/XS-MLVP/UCAgent --skill sva-gen

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires jinja2, and includes scripts (resource) components.

What problem does it solve?

This skill guides translating .formal_records.yaml's sva_body placeholders into complete SVA assertion code used for formal verification.

Core Features & Use Cases

  • Data-driven SVA generation from YAML: convert placeholders into fully formed SVA properties.
  • Update workflow with update_sva_body.py: inject code into YAML and keep SV files read-only, ensuring reproducibility.
  • Automation and validation: trigger the Check tool to render checker.sv and wrapper.sv and validate coverage.

Quick Start

Update the SVA body with update_sva_body.py and run the Check workflow to render the latest checker and wrapper.

Frequently Asked Questions about sva-gen

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate SystemVerilog assertions from YAML for formal verification?

You can generate SystemVerilog assertions from YAML by converting stored sva_body placeholders into complete SVA properties. This workflow uses update_sva_body.py to inject code and renders the final SV files automatically.

What is the best way to automate SVA property generation from YAML checkpoints?

The best way to automate SVA property generation is using a template-driven workflow that reads YAML checkpoints and renders them into formal verification assertions. This prevents manual edits and ensures reproducible SV file formatting.

Why should I avoid manual edits to generated SystemVerilog assertion files?

You should avoid manual edits to generated SystemVerilog files because the workflow enforces read-only SV files. Direct modifications bypass YAML-driven template logic and break the reproducible update_sva_body.py validation flow.

Can I use a script to inject SVA code into YAML and validate formal coverage?

Yes, you can use update_sva_body.py to inject SVA code into YAML and trigger the Check tool. This validates formal coverage by rendering checker.sv and wrapper.sv directly from the YAML data.

Does the SVA generation workflow require Jinja2 dependencies?

Yes, the SVA generation workflow requires Jinja2 dependencies to enforce template-driven SVA logic. It uses this engine to render YAML-stored placeholders into fully formed SystemVerilog assertions for formal checks.