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static-bug-analysis

Analyze RTL designs for static bugs using FG/FC/CK taxonomy.

207|45|Updated May 27, 2025
Search Tags:#verification#code-quality#static-analysis#bug-analysis#rtl#verilog
One-click install
npx skills add https://github.com/XS-MLVP/UCAgent --skill static-bug-analysis
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: static-bug-analysis
Source: https://github.com/XS-MLVP/UCAgent/tree/main/ucagent/lang/zh/skills/unitytest/static-bug-analysis
Command: npx skills add https://github.com/XS-MLVP/UCAgent --skill static-bug-analysis

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) components.

What problem does it solve?

RTL designs often harbor subtle bugs undetected by informal reviews; this skill provides a structured workflow to perform static bug analysis on DUT RTL sources.

Core Features & Use Cases

  • Step-based static analysis guided by FG/FC/CK taxonomy present in DUT_functions_and_checks.md.
  • Generates structured bug reports with code context automatically appended to DUT_static_bug_analysis.md.
  • Use Case: Verification engineer audits RTL modules under DUT RTL/, identifies potential issues like state-machine gaps, boundary conditions, timing hazards, interface protocol concerns, and records them for remediation.

Quick Start

Run the static bug analysis workflow on DUT RTL sources to identify potential bugs and append them to the DUT_static_bug_analysis.md via RunSkillScript.

Frequently Asked Questions about static-bug-analysis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
What is static bug analysis in RTL design and when should I use it?▼

Perform static bug analysis on RTL sources by running the analysis workflow, which cross-references FG/FC/CK taxonomy points from your DUT_functions_and_checks.md file to identify potential issues and append structured bug report entries to DUT_static_bug_analysis.md.

How do I perform static bug analysis on Verilog RTL code?▼

Perform static bug analysis on RTL sources by running the analysis workflow, which cross-references FG/FC/CK taxonomy points from your DUT_functions_and_checks.md file to identify potential issues and append structured bug report entries to DUT_static_bug_analysis.md.

Do I need a specific taxonomy file to audit RTL state-machine integrity and boundary conditions?▼

Yes, static bug analysis detects state-machine gaps, boundary conditions, timing hazards, and interface protocol concerns in RTL sources, generating structured bug reports with code context for remediation.

What types of RTL bugs can static analysis detect without simulation?▼

Static analysis identifies state-machine gaps, boundary conditions, timing hazards, and interface protocol issues by cross-referencing FG/FC/CK points with DUT function definitions, systematically catching RTL bugs that informal code reviews often miss.

Does static bug analysis work with both Verilog and VHDL RTL projects?▼

Yes, static bug analysis is applicable to both Verilog and VHDL RTL projects across development and verification pipelines, auditing code for state-machine integrity and interface protocols without requiring external simulation dependencies.

How are identified RTL bugs documented during the static analysis workflow?▼

Identified RTL bugs are documented as structured bug report entries with status and code snippets, automatically appended to DUT_static_bug_analysis.md via RunSkillScript to provide clear context for verification engineers during remediation.

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