Apply a formal review checklist to Verilog RTL code and return PASS/WARN/FAIL results.
npx skills add https://github.com/pjy4617/pjy-claude-skill --skill rtl-review
Please help me install this Agent Skill. Skill: rtl-review Source: https://github.com/pjy4617/pjy-claude-skill/tree/main/plugins/vivado/skills/rtl-review Command: npx skills add https://github.com/pjy4617/pjy-claude-skill --skill rtl-review
This skill defines an RTL code review checklist that the rtl-reviewer agent uses as a reference during code reviews requested by users who say "코드 리뷰", "RTL 검증", "린트", or "리뷰해줘".
Invoke rtl-review by supplying a Verilog RTL module and ask the rtl-reviewer agent to apply the checklist to produce a PASS/WARN/FAIL report.
High-intent search queries and answers about installing and using this skill.
To perform a Verilog RTL code review, supply the module to the rtl-reviewer agent which applies a formal checklist to evaluate synthesizability, coding style, and testbench quality, returning structured PASS/WARN/FAIL results.
An RTL linting checklist covers synthesizability, coding style, port and hierarchy consistency, timing and resource usage, and testbench quality to identify code quality issues in Verilog designs.
Yes, you can delegate the review work to an agent that evaluates Verilog port and hierarchy alignment against formal review criteria, ensuring consistency before module integration.
The best way to audit a Verilog module is applying a formal review checklist via an agent that evaluates synthesizability and timing, returning a PASS/WARN/FAIL report to ensure adherence to quality standards.
Yes, RTL review includes testbench quality as part of its formal evaluation checklist, allowing the agent to identify issues in verification setup alongside synthesizability and timing constraints.
A Verilog RTL review returns a FAIL result when the agent identifies critical code quality issues in synthesizability, port consistency, or timing that violate the formal review checklist criteria.
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