rtl-agent-team
Automated RTL design, verification, and silicon signoff pipeline
All Skills in This Repository (94)
Pure Emerald Level Indicatorsp1-spec-research
Refine ambiguous hardware specifications into validated requirements with acceptance criteria.
rat-init-project
Initialize RTL project workspaces with standardized directories, templates, and EDA scripts.
rtl-ipxact-gen
Generate IEEE 1685-2014 IP-XACT XML descriptors from RTL module definitions.
rtl-p5s-perf-verify
Measure RTL throughput, latency, and stall cycles against BFM baselines.
rtl-p5-verify-team
Orchestrate end-to-end RTL verification workflows across multiple modules with dependency-aware task graphs.
rtl-p5a-functional-closure
Coordinate Phase 5A functional verification closure across RTL modules, blocks, and top-level integration.
rat-p1p3-spec-uarch-policy
Enforce phase-gate policy and governance for the Phase 1→3 RTL design pipeline.
rtl-p5-verify
Orchestrate three-stage Phase 5 RTL verification with lint, formal, CDC, and regression reports.
syn-tool-profiles
Generate replayable synthesis profiles for yosys, dc_shell, and genus.
rat-p4p5-impl-verify-policy
Enforce Phase 4 to 5 gate criteria before RTL verification.
uvm
Standardize UVM testbench class naming, factory usage, and phase handling.
rtl-p5s-sva-check
Extract SystemVerilog assertions from RTL and run SymbiYosys formal verification.
Frequently Asked Questions
FAQPage SchemaHow to install rtl-agent-team?▼
Run `npx skills add babyworm/rtl-agent-team --all -g -y` in your terminal to install the full skill set globally. Afterwards, run the rat-setup skill once per machine to audit your EDA toolchain.
What does the 6-phase RTL pipeline cover?▼
It runs Research, Architecture, Microarchitecture, RTL implementation, Verification, and Design Note phases, each protected by artifact and quality gates. You can run it end-to-end with rat-auto-design or invoke individual phase skills.
Which EDA tools does it support?▼
It works with open-source tools like Verilator, Yosys, Verible, slang, cocotb, and SymbiYosys, plus commercial tools such as VCS, Xcelium, Questa, Design Compiler, Genus, and SpyGlass. Missing tools can fall back to a Docker-based environment.
Can it verify RTL automatically after changes?▼
Yes. Hooks enforce a mandatory lint, testbench, and simulation cycle after any RTL edit, so a change is never considered done on lint alone. Coverage, CDC, formal, and protocol checks run as separate verification categories.
Do I need hardware design experience to use it?▼
Basic RTL knowledge helps, but the pipeline guides you through spec clarification, architecture decisions, and verification with structured questions and review reports. Domain expert agents answer codec, protocol, and signal-processing questions on demand.
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