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amoslee2026
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bb-invoke-netgen

Compare schematic Verilog netlists with layout SPICE extractions using Netgen LVS.

41|9|Updated May 22, 2026
Search Tags:#verilog#pd#lvs#netgen#asap7#lvs-report#spice
One-click install
npx skills add https://github.com/amoslee2026/Babel --skill bb-invoke-netgen
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: bb-invoke-netgen
Source: https://github.com/amoslee2026/Babel/tree/main/.claude/skills/bb-invoke-netgen
Command: npx skills add https://github.com/amoslee2026/Babel --skill bb-invoke-netgen

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

This skill automates LVS-based verification by comparing a schematic netlist against a layout-derived SPICE netlist using Netgen LVS, delivering a clear pass/fail verdict to accelerate signoff.

Core Features & Use Cases

  • End-to-end LVS workflow: render a Netgen setup, execute LVS, and parse the resulting report into a structured result.
  • ASAP7-aware verification: supports common ASAP7 layouts and reports discrepancies to guide fixes.
  • Use cases include post-extraction signoff checks, regression verification across design iterations, and automated quality gates in the PD flow.

Quick Start

Run the bb-invoke-netgen skill with your schematic_netlist, layout_netlist, and setup_file to perform an LVS check and generate a results JSON.

Frequently Asked Questions about bb-invoke-netgen

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate LVS signoff comparing a Verilog netlist with a SPICE extraction?▼

You can automate LVS signoff by running a Netgen comparison between your schematic Verilog netlist and layout SPICE extraction, which outputs a structured JSON containing the match status and discrepancies. This streamlines post-extraction verification.

What inputs are required to run a Netgen LVS check on ASAP7 layouts?▼

Running a Netgen LVS check requires five inputs: schematic_netlist, layout_netlist, setup_file, top, and design_name. Providing these allows the verification process to generate a structured match or mismatch verdict for your ASAP7 layout.

Can I use this LVS verification process for regression checks across design iterations?▼

Yes, you can use this LVS verification process for regression verification across design iterations. By invoking the Netgen comparison explicitly, you can perform quick post-extraction checks and integrate automated quality gates into your physical design flow.

How does Netgen parse LVS report discrepancies into a structured format?▼

Netgen parses the resulting LVS report into a structured JSON format that clearly identifies the match status and lists specific discrepancies. This allows you to quickly pinpoint mismatches between your schematic and layout netlists to guide fixes.

Does this LVS workflow support both explicit invocation and automated PD flow integration?▼

Yes, this LVS workflow supports both automated physical design flow integration and explicit invocation for quick checks. It renders a Netgen setup, executes the LVS comparison, and parses the report to deliver a clear pass or fail signoff verdict.

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