amoslee2026
Community@amoslee2026 · Universe Zero
Agent Skills by amoslee2026
Showing 32 vetted skills indexed across 1 GitHub repositories.
amoslee2026<skill-name-kebab-case>
Provide a frontmatter-driven Skill Unit template with optional resource directories.
amoslee2026bb-invoke-yosys
Automate end-to-end RTL synthesis workflows with Yosys and parallel execution.
amoslee2026bb-collect-coverage
Aggregate Verilator line, branch, and toggle coverage from coverage.dat and simulation logs.
amoslee2026bb-invoke-abc
Automate ABC-driven logic optimization on Yosys BLIF outputs.
amoslee2026bb-trace-signal-path
Trace signal paths through AST JSON from source to sink.
amoslee2026bb-arch
Convert rough architectural ideas into formal chip architecture specification documents.
amoslee2026bb-create-floorplan
Generates Magic floorplan TCL from MAS JSON and netlist data.
amoslee2026bb-gate
Automate pass/fail quality gates for RTL, synthesis, PD, and test artifacts with JSON output.
amoslee2026bb-spec-review
Review PRD, arch_spec, and MAS documents for consistency and feasibility gaps.
amoslee2026bb-mas
Generate chiplet MAS, FSM, datapath, verification, and DFT documentation from architecture specs.
amoslee2026bb-invoke-qrouter
Detail-route placed DEF files using QRouter to produce routed DEF.
amoslee2026bb-invoke-verilator
Compile RTL and testbench, run Verilator simulation, and produce logs, coverage, and VCD.
amoslee2026bb-search-protocol
Search wiki/protocols for matching document paths and summaries.
amoslee2026bb-rtl-coder
Translate MAS, FSM, and datapath specifications into synthesizable SystemVerilog RTL.
amoslee2026bb-code-review
Review RTL MAS designs for defects, timing risk, and alignment.
amoslee2026bb-find-module-deps
Parse RTL designs to generate file_list.f with leaf modules first.
amoslee2026bb-list-issues
Aggregate open design handoffs and synchronize them with GitHub issues.
amoslee2026bb-invoke-klayout
Automate KLayout GDSII export, DRC checks, and signoff verification.
amoslee2026bb-parse-ast
Parse SystemVerilog RTL into a unified AST with modules, ports, instances, and parameters.
amoslee2026bb-invoke-magic
Automate Magic PD tasks with batch TCL generation and JSON result parsing.
amoslee2026bb-invoke-opensta
Automate OpenSTA multi-corner timing analysis and parse results into JSON.
amoslee2026bb-get-interface-template
Extract interface and ports sections from wiki markdown into JSON.
amoslee2026bb-check-lint
Lint HDL sources with Verible and output a JSON report.
amoslee2026bb-close-issue
Move handoff records to a closed archive and log the action.