bb-invoke-verilator

Automating Verilator RTL simulation involves rendering compile scripts, executing the testbench, and parsing logs to produce sim results, coverage data, and VCD waveforms. This workflow applies when testbenches are ready and RTL changes require regression runs to validate correctness.

Running automated Verilator testbench regressions requires Verilator 5.012 installed, provided automation scripts rendered and executed, and design-specific sim_results directories for reading and writing simulation logs, coverage data, and VCD outputs.

Phase-driven RTL simulation automation works by rendering the Verilator script, executing it to compile RTL and testbench code, and parsing the resulting logs to output a structured result containing sim logs, coverage.dat, and VCD waveform traces.

Yes, this automation is triggered by verification tasks specifically for regression testing after RTL fixes. It compiles the updated RTL and ready testbenches, runs the simulation, and collects logs and coverage to validate correctness.

Automated Verilator simulations generate sim logs, coverage.dat files for downstream analysis, and VCD waveform traces. These artifacts are written to design-specific sim_results directories for validating correctness and coverage.

Yes, automated RTL simulation requires Verilator 5.012. The provided scripts under the scripts directory depend on this specific version to properly render, run, and parse the simulation results.