Automate OpenSTA multi-corner timing analysis and parse results into JSON.
npx skills add https://github.com/amoslee2026/Babel --skill bb-invoke-opensta
Please help me install this Agent Skill. Skill: bb-invoke-opensta Source: https://github.com/amoslee2026/Babel/tree/main/.claude/skills/bb-invoke-opensta Command: npx skills add https://github.com/amoslee2026/Babel --skill bb-invoke-opensta
OpenSTA timing analysis is essential for validating WNS/ TNS across synthesis and post-PD flows, but doing multi-corner signoff manually is time-consuming and error-prone.
Provide netlist, top_module, sdc_path, and tech_lib (or a corner map) to run OpenSTA timing signoff across defined corners.
High-intent search queries and answers about installing and using this skill.
You can automate OpenSTA multi-corner timing signoff by providing a netlist, top module, SDC path, and tech library. The tool renders per-corner TCL scripts, executes them, and parses WNS/TNS results into a JSON report.
Running multi-corner timing signoff requires a design netlist, top module name, SDC path, and tech library or corner map. These inputs enable the tool to validate WNS/TNS across synthesis and post-PD flows.
Yes, OpenSTA timing signoff supports ASAP7 technology corners. The automation tool applies multi-corner timing checks using ASAP7 corner definitions for synthesis and post-PD design flows.
Automated OpenSTA reporting parses WNS and TNS results by extracting timing data from execution logs into a structured JSON report. This format enables quick timing gap analysis and triggers re-runs in synthesis workflows.
Integrate OpenSTA timing checks into a post-PD workflow by automating multi-corner signoff with TCL rendering scripts. This validates WNS/TNS and triggers synthesis or PD re-runs when timing gaps are detected.
Manual multi-corner timing signoff is time-consuming and error-prone when validating WNS/TNS across synthesis and post-PD flows. Automating OpenSTA TCL execution and JSON log parsing eliminates these manual errors.
amoslee2026Generate MAS-based SDC timing constraints and validate them with OpenSTA.
amoslee2026Automate pass/fail quality gates for RTL, synthesis, PD, and test artifacts with JSON output.
ShenShan123Automate EDA signoff from RTL to GDS with DRC, LVS, and RCX verification.
chuanseng-ngAutomate multi-corner timing analysis and sign-off for chip designs.
