Automate end-to-end RTL synthesis workflows with Yosys and parallel execution.
npx skills add https://github.com/amoslee2026/Babel --skill bb-invoke-yosys
Please help me install this Agent Skill. Skill: bb-invoke-yosys Source: https://github.com/amoslee2026/Babel/tree/main/.claude/skills/bb-invoke-yosys Command: npx skills add https://github.com/amoslee2026/Babel --skill bb-invoke-yosys
Automates the end-to-end RTL synthesis workflow by orchestrating a Yosys-based mapping to ASAP7 with an LLM-managed control plane, enabling rapid iteration for complex chip designs.
Provide a synthesis config for designs and run the parallel Yosys-based RTL synthesis workflow.
High-intent search queries and answers about installing and using this skill.
Automating RTL synthesis for multiple designs involves generating per-design configs, rendering TCL scripts, executing parallel Yosys flows, and parsing QoR results. This Skill orchestrates that entire end-to-end workflow with LLM-managed control and strict input validation.
LLM-driven synthesis orchestration uses an LLM to manage the control plane of Yosys flows. It applies a configurable parallel strategy to maximize resource utilization, executing multiple design mappings concurrently and feeding structured results back for iteration.
Yes, mapping RTL to ASAP7 using Yosys is fully supported. The workflow parses QoR metrics from the synthesis run and provides structured results, enabling automated iterative feedback loops to fix RTL or architecture issues and re-run synthesis.
Parallel Yosys synthesis requires proper environment sourcing and version checks before execution. The workflow implements strict input validation and error handling to ensure the environment is correctly configured before running the synthesis flows.
The best way to parse QoR results is through an automated workflow that extracts metrics from Yosys logs and provides structured data. This Skill handles QoR parsing directly, outputting results ready for downstream STA and PD analysis.
Automated RTL synthesis fails during parallel execution when environment sourcing or version checks are incomplete. This workflow enforces strict input validation and configurable parallel strategies to handle errors and maximize resource utilization safely.
ShenShan123Detect, install, and verify open-source EDA tools for RTL-to-GDS flows.
KishoreDamamGuide RTL authors in preparing synthesizable SystemVerilog for Vivado and Synopsys DC/Genus.
jcastillotxDelegate tasks to suitable AI subagents with parallel execution and logging.
Shinei-Nouzen-ArchIdentify optimal Vivado synthesis strategies and attribute configurations for QoR.
