Parse RTL designs to generate file_list.f with leaf modules first.
npx skills add https://github.com/amoslee2026/Babel --skill bb-find-module-deps
Please help me install this Agent Skill. Skill: bb-find-module-deps Source: https://github.com/amoslee2026/Babel/tree/main/.claude/skills/bb-find-module-deps Command: npx skills add https://github.com/amoslee2026/Babel --skill bb-find-module-deps
Scan RTL directories to derive a module-to-file mapping and a module instantiation graph, then topologically sort the modules and emit file_list.f (leaves first, top last) for Yosys/Verilator workflows.
Invoke bb-find-module-deps with rtl_dir set to designs/<name>/rtl and top_module set to the top module to generate file_list.f.
High-intent search queries and answers about installing and using this skill.
To generate a topologically sorted Verilog file list for Yosys or Verilator, you can use a dependency analysis tool to scan RTL directories, resolve module instantiations, and emit a file_list.f with leaf modules first and the top module last.
Ordering SystemVerilog files by module dependencies involves parsing designs to build a module-to-file mapping and an instantiation graph, then applying a topological sort to output an ordered file_list.f ready for synthesis workflows.
Resolving cyclic dependencies when parsing RTL module instantiations requires a dependency analysis pipeline that detects cycles during the topological sort phase, ensuring the output file list accurately represents the module hierarchy without breaking the synthesis flow.
Yes, you can automatically extract include and define directives for a Verilog file list by scanning RTL directories to derive module definitions and instantiations, outputting an ordered file_list.f that integrates these directives for downstream tools.
Yes, this RTL dependency analysis tool works with nested submodules across multiple directories by scanning the specified designs/<name>/rtl path, resolving inter-module instantiations, and handling multiple submodules to output a correctly ordered file list.
A topological sort might fail to identify the correct top module in your RTL design if the top_module parameter is not explicitly set or if the RTL directory path does not match the expected designs/<name>/rtl structure required for accurate module-to-file mapping.
dtsongReview Verilog, SystemVerilog, and VHDL RTL designs for security vulnerabilities.
londeyEnforce consistent Verilog and SystemVerilog coding style for Verilator linting and Yosys synthesis.
babywormEnforce SystemVerilog coding conventions on generated and modified RTL files.
curiositechValidate directed acyclic graphs and produce topological orders with cycle reports.
