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bb-parse-ast

Parse SystemVerilog RTL into a unified AST with modules, ports, instances, and parameters.

41|9|Updated May 22, 2026
Search Tags:#tracing#parsing#ast#rtl#cdc#verilog
One-click install
npx skills add https://github.com/amoslee2026/Babel --skill bb-parse-ast
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: bb-parse-ast
Source: https://github.com/amoslee2026/Babel/tree/main/.claude/skills/bb-parse-ast
Command: npx skills add https://github.com/amoslee2026/Babel --skill bb-parse-ast

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

Parses SystemVerilog RTL into a standard AST to enable cross-tool CDC checks, signal-path tracing, and module dependency analysis.

Core Features & Use Cases

  • Multi-backend support (pyverilog, verible, slang) with automatic downgrade to maximize AST generation success across SV constructs.
  • Produces a consistent AST schema covering modules, ports, instances, and parameters for downstream verification tasks.
  • Use case: before CDC or tracing tasks, extract a reliable AST for cross-reference and dependency analysis.

Quick Start

Provide file_list and design_name to bb-parse-ast to generate the AST for downstream analysis.

Frequently Asked Questions about bb-parse-ast

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I parse SystemVerilog RTL into an AST for CDC tracing?▼

bb-parse-ast parses SystemVerilog RTL into a unified AST for CDC tracing by requiring a file_list and design_name, outputting modules, ports, instances, and parameters in a stable schema.

What is the best way to handle unsupported SystemVerilog constructs during AST generation?▼

Handling unsupported SystemVerilog constructs relies on automatic fallback across pyverilog, verible, and slang backends to maximize AST generation success when primary parsing fails.

Does this AST parsing tool support multiple backends like pyverilog and verible?▼

Yes, this AST parsing tool supports pyverilog, verible, and slang backends with an automatic downgrade path to maximize parsing success across different SystemVerilog constructs.

How do I extract module dependencies and signal paths from SystemVerilog?▼

Extracting module dependencies and signal paths requires parsing SystemVerilog RTL into a consistent AST schema, which enables cross-reference and dependency analysis before downstream verification tasks.

What inputs do I need to generate an AST for module dependency analysis?▼

Generating an AST for module dependency analysis requires providing a file_list containing RTL paths and a design_name to produce a stable schema covering modules, ports, instances, and parameters.

When do I need to parse RTL into an AST before running CDC checks?▼

Parsing RTL into an AST is required before running CDC checks, signal-path tracing, or dependency queries to extract a reliable representation for cross-reference and downstream verification analysis.

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