Translate MAS, FSM, and datapath specifications into synthesizable SystemVerilog RTL.
npx skills add https://github.com/amoslee2026/Babel --skill bb-rtl-coder
Please help me install this Agent Skill. Skill: bb-rtl-coder Source: https://github.com/amoslee2026/Babel/tree/main/.claude/skills/bb-rtl-coder Command: npx skills add https://github.com/amoslee2026/Babel --skill bb-rtl-coder
This tool automates the translation of MAS, FSM, and datapath specifications into synthesizable SystemVerilog RTL, dramatically shortening development cycles and reducing human error.
Prepare MAS/FSM/datapath inputs for the target module and run the bb-rtl-coder to generate synthesizable SystemVerilog RTL from those specifications.
High-intent search queries and answers about installing and using this skill.
To generate synthesizable SystemVerilog RTL from MAS documents, you prepare your MAS, FSM, and datapath specifications as inputs and run the generation process to translate them into RTL code while preserving port mappings and timing constraints.
REQ-level traceability in automated RTL generation is the mechanism of injecting SPEC headers and requirement mappings directly into the SystemVerilog output, ensuring end-to-end verification and compliance between the original MAS specifications and the generated code.
Yes, you can inject SVA checks into SystemVerilog during RTL generation. The process automatically embeds SystemVerilog Assertions to support end-to-end verification and ensures the generated RTL complies with the specified design requirements.
Yes, automated RTL generation supports iterative refinement by integrating with code-review pipelines to detect, fix, and push RTL changes across design phases, ensuring continuous quality checks during the generation process.
The best way to translate FSM and datapath specifications into SystemVerilog is using an AI-native chiplet design workflow that automates the translation, injects SVA checks, and maintains REQ-level traceability to reduce human error and shorten development cycles.
No, you do not need to manually verify timing constraints when generating RTL from MAS specs. The automated translation process ensures that port mappings and timing constraints are preserved directly in the synthesizable SystemVerilog output.
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