skills.rest
tangyangchao578-art
tangyangchao578-artCOMMUNITY
Explore all skills by this author →
GitHub

systemverilog

Enforce synthesizable SystemVerilog design patterns with interfaces and typedefs.

2|1|Updated Apr 6, 2026
Search Tags:#interfaces#verification#generate#systemverilog#rtl-design#always_ff#typedef
One-click install
npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill systemverilog-tangyangchao578-art
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: systemverilog
Source: https://github.com/tangyangchao578-art/icer_skill_package/tree/main/skills/systemverilog
Command: npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill systemverilog-tangyangchao578-art

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

SystemVerilog usage guidance delivers structured patterns and best practices to write robust, maintainable SV code for both design and verification.

Core Features & Use Cases

  • Synthesizable design patterns using always_ff and always_comb
  • Interfaces and modports for clean module connectivity
  • Parameterization, generate blocks, typedef/struct/enum usage
  • Verification-oriented practices with clear separation of concerns
  • Practical examples across common design and verification tasks

Quick Start

Enable SystemVerilog usage skill to start applying best practices immediately.

Frequently Asked Questions about systemverilog

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write synthesizable SystemVerilog using always_ff and always_comb?▼

Use always_ff for sequential logic and always_comb for combinational logic to enforce clean coding standards and prevent inferred latches. This separation ensures synthesizable patterns and maintainable RTL design.

What is the best way to use interfaces and modports for module connectivity in SystemVerilog?▼

The best way to manage module connectivity is using SystemVerilog interfaces and modports to bundle signals and define directional access, creating clear verification-oriented structures and reducing wiring errors.

How do I use typedef, struct, and enum definitions across multiple modules?▼

Define SystemVerilog typedef, struct, and enum types in a shared package to enable consistent type usage across modules. This enforces clean coding standards and clear verification-oriented structures.

When do I need generate blocks and parameterization in RTL design?▼

Use SystemVerilog generate blocks and parameterization when you need conditional instantiation or scalable RTL design. They enable reusable, synthesizable patterns for varying data widths or module configurations.

Does this approach support verification tasks as well as RTL design?▼

Yes, this SystemVerilog approach supports both RTL design and verification tasks by enforcing clear separation of concerns, using interfaces, and maintaining verification-oriented structures for robust testbenches.

Related Skills

Explore More Software Engineering Skills→
ArabelaTsoArabelaTso
142

rtl-property-inference

Infer formal correctness properties from Verilog/SystemVerilog RTL and generate SVA assertions.

Community
Advanced
codejunkie99codejunkie99
3

GateFlow Behavior

Automate SystemVerilog linting, simulation, and analysis task orchestration.

Community
Basic
rajivhasija79-bitrajivhasija79-bit
3

dv-assertions

Generate SystemVerilog Assertions from testplans and TB data for DV environments.

Community
Advanced
ulf1ulf1

324-pytorch-to-vhdl

Convert PyTorch neural networks into synthesizable VHDL with fixed-point quantization.

Community
Advanced