tangyangchao578-art
Community@tangyangchao578-art
Agent Skills by tangyangchao578-art
Showing 11 vetted skills indexed across 1 GitHub repositories.
tangyangchao578-artfunctional-safety-analysis
Automate functional safety analysis and FMEDA design for ISO 26262 compliance.
tangyangchao578-artsystemverilog
Enforce synthesizable SystemVerilog design patterns with interfaces and typedefs.
tangyangchao578-artarchitecture-design
Define and optimize chip architectures from requirements to modular decomposition.
tangyangchao578-artboard-bringup
Automate FPGA/board bringup verification from static checks to system tests.
tangyangchao578-arttiming-analysis
Analyze timing violations across corners with MMMC and OCV considerations.
tangyangchao578-arteda-scripting
Orchestrate TCL, Python, and Makefile tasks for EDA IC design workflows.
tangyangchao578-artuvvm-verification
Builds IEEE-compliant UVM verification environments from validation plans to functional coverage.
tangyangchao578-artphysical-design
Guide digital IC physical design from floorplanning to GDSII signoff.
tangyangchao578-artassertion-based-verification
Guide engineers to implement assertion-based verification with SVA properties.
tangyangchao578-artrtl-coding
Guide engineers to write clean, synthesizable SystemVerilog RTL code.
tangyangchao578-artpower-analysis
Analyze dynamic and static power, IR drop, and EM violations in IC designs.