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timing-analysis

Analyze timing violations across corners with MMMC and OCV considerations.

2|1|Updated Apr 6, 2026
Search Tags:#setup#timing-analysis#sta#hold#mmmc#ocv
One-click install
npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill timing-analysis-tangyangchao578-art
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: timing-analysis
Source: https://github.com/tangyangchao578-art/icer_skill_package/tree/main/skills/timing-analysis
Command: npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill timing-analysis-tangyangchao578-art

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Static timing analysis decodes timing violations, identifies critical paths, and provides actionable fixes to accelerate convergence and robust sign-off.

Core Features & Use Cases

  • WNS/TNS diagnosis across setup and hold violations for multi-corner scenarios.
  • MMMC analysis and CPPR/OCV considerations to validate timing across process/voltage/temperature variations.
  • Structured workflows and actionable recommendations for layout, CTS, and routing to drive timing convergence.

Quick Start

Run a complete static timing analysis pass on a design to identify critical paths and containment strategies.

Frequently Asked Questions about timing-analysis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I diagnose setup and hold timing violations across multiple corners?▼

Static timing analysis decodes setup and hold timing violations by evaluating WNS and TNS across multi-corner scenarios. It interprets critical paths and provides actionable fixes to accelerate convergence and ensure robust sign-off.

How does MMMC analysis handle OCV considerations for timing sign-off?▼

MMMC analysis validates timing across process, voltage, and temperature variations by applying OCV and CPPR considerations. This ensures accurate cross-corner evaluation and robust sign-off for complex chip design workflows.

What inputs do I need to run a complete static timing analysis pass?▼

Running static timing analysis requires the design netlist, libraries, constraints, and parasitics as inputs. It processes these to output comprehensive timing reports, identify violations, and recommend actionable containment strategies.

What's the best way to guide layout and routing fixes for critical path timing convergence?▼

Static timing analysis provides structured workflows and actionable recommendations for layout, CTS, and routing. This directly guides the fixes needed to resolve critical path violations and drive end-to-end timing convergence.

Can I use static timing analysis for cross-corner validation without dedicated CPPR checking?▼

Static timing analysis explicitly includes CPPR and OCV considerations to validate timing accurately. Omitting these checks during cross-corner analysis risks inaccurate timing predictions and fails robust sign-off requirements.

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