physical-design

Name: physical-design
Availability: InStock
Author: tangyangchao578-art

Guide digital IC physical design from floorplanning to GDSII signoff.

2|1|Updated Apr 6, 2026

Search Tags:#routing #placement #cts #pdn #floorplan #timing-closure

Ready to run

npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill physical-design

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: physical-design
Source: https://github.com/tangyangchao578-art/icer_skill_package/tree/main/skills/physical-design
Command: npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill physical-design

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Digital IC teams face the challenge of turning architectural intent into manufacturable layouts. This Skill provides end-to-end guidance for physical design workflows, from floorplanning to GDSII, including problem diagnosis, optimization strategies, and best practices to reduce iteration cycles and improve tapeout success.

Core Features & Use Cases

Floorplanning, placement, CTS, routing, and signoff readiness across process nodes.
PDN/DFM considerations, IR drop analysis, power integrity optimization.
Practical workflows and best practices for faster, more reliable tapeouts.

Quick Start

Begin with a new floorplan and progress through placement, CTS, routing, timing closure, and signoff.

Frequently Asked Questions about physical-design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I run the full-chip physical design workflow from floorplanning to GDSII?▼

Full-chip physical design workflow progresses from floorplanning through placement, CTS, routing, timing closure, and signoff to generate GDSII, reducing iteration cycles for faster tapeout.

What is the best way to fix IR drop and power integrity issues during PDN optimization?▼

PDN optimization for power integrity and IR drop requires analyzing floorplan constraints and applying DFM validation strategies to meet design verification requirements across nodes.

How do I achieve timing closure and signoff readiness for digital chip projects at 28nm to 7nm nodes?▼

Timing closure and signoff readiness requires iterating placement, CTS, routing, and DFM validation across 28nm to 7nm nodes to pass LVS/DRC checks using standard EDA tools.

Does this physical design workflow support LVS/DRC checks and DFM validation using standard EDA tools?▼

Yes, the physical design workflow supports LVS/DRC checks and DFM validation using standard EDA tools to ensure signoff readiness and manufacturable layouts.

Can I use this physical design workflow for floorplanning and CTS across different process nodes?▼

Yes, physical design workflow applies to floorplanning and CTS across process nodes from 28nm to 7nm, ensuring reliable tapeout and power integrity optimization.

Why does timing closure fail during routing and how can I reduce iteration cycles?▼

Timing closure fails during routing due to unoptimized placement or CTS; applying end-to-end physical design workflows and best practices reduces iteration cycles and improves tapeout success.