code-review-riscv

To check RISC-V assembly for ABI violations, review syntax, operands, immediate ranges, register conventions, memory alignment, and control flow. Validating calling conventions and CSR usage ensures correctness across standalone assembly files, inline asm blocks, and small modules.

Common RISC-V inline asm pitfalls include misalignment, stack corruption, clobbered registers, and illegal immediates. Analyzing instruction operands, saved versus temporary register usage, and stack alignment prevents these errors and maintains ABI compliance.

RISC-V assembly review covers both RV32I and RV64I base ISAs alongside common extensions like M, A, F, D, and C. It validates platform-specific differences, ABI variants, and instruction correctness across these distinct architectures.

Validating CSR operations in RISC-V involves checking privilege levels, atomicity, and field types. Assembler directives are verified for correct section placement, alignment, symbol visibility, and data placement to ensure proper module assembly.

The best way to verify stack alignment and register conventions is to audit saved versus temporary register usage and stack frame boundaries. Checking memory access alignment, sign extension, and offset limits ensures calling convention adherence.

RISC-V assembly fails with illegal immediates when immediate ranges exceed ISA limits, and misalignment occurs when memory access lacks proper boundaries. Reviewing instruction operands, offset limits, and data placement resolves these constraint violations.