Implement and optimize CuTe DSL GPU kernels across NVIDIA architectures.
npx skills add https://github.com/vipshop/cache-dit --skill cute-dsl-kernel
Please help me install this Agent Skill. Skill: cute-dsl-kernel Source: https://github.com/vipshop/cache-dit/tree/main/.copilot/skills/cute-dsl-kernel Command: npx skills add https://github.com/vipshop/cache-dit --skill cute-dsl-kernel
Developers need a reliable, reference-backed workflow to write, port, debug, and integrate CuTe DSL GPU kernels that meet correctness and performance expectations across multiple NVIDIA GPU generations. This Skill centralizes the CuTe DSL API snapshots, architecture-specific optimization guidance, profiling advice, and validation requirements so engineers do not guess APIs or optimization strategies from memory.
Implement a tiled GEMM CuTe DSL kernel targeting SM100, consult the bundled cute.md and sm100-optimization-guide.md for tiling and TMA usage, compile, and validate numerics and performance against a PyTorch baseline.
High-intent search queries and answers about installing and using this skill.
To build a CuTe DSL GPU kernel, design your tiled operations by consulting bundled API snapshots and architecture-specific optimization notes, then compile and validate the implementation against a PyTorch baseline. The workflow covers designing, testing, and integrating kernels across SM80 to SM120 architectures.
The recommended profiling workflow for CuTe DSL kernels starts with nsys to identify high-level bottlenecks, followed by ncu for detailed kernel-level analysis. This sequence includes shape-reduction and synchronization diagnostics specifically tailored for debugging pipelined or shared-memory GPU kernels.
Yes, CuTe DSL provides per-generation optimization guidance for SM89, SM90, SM100, SM103, and SM120 architectures. This includes specific TMEM, TMA, and WGMMA guidance to interpret profiling results and optimize GPU kernel execution across supported NVIDIA GPU generations.
You validate CuTe DSL kernel correctness by implementing unit tests that compare numerical outputs against a PyTorch baseline. The implementation workflow includes step-by-step testing and validation requirements to ensure your GPU kernel meets expected correctness standards before integration.
Shared-memory CuTe DSL kernel synchronization issues often stem from incorrect pipelining or barrier management, identifiable through ncu profiling. The Skill provides actionable synchronization diagnostics and shape-reduction checks to isolate and resolve these specific GPU kernel execution bottlenecks.
Yes, CuTe DSL supports both JIT and AOT compilation workflows for GPU kernels. The Skill provides API reference bundles and runtime helpers that facilitate rapid lookup and integration when compiling kernels for high-performance execution across multiple NVIDIA GPU generations.
dotruruAutomates development, debugging, and optimization of CUTLASS and CuTeDSL GPU kernels using local sources.
NVIDIAWrite GPU kernels with NVIDIA CuTe DSL using Python decorators.
RomaosirOptimizes and debugs CUDA kernels for NVIDIA B200 using compute-sanitizer, nsys, and ncu.
yo-stevenCoordinates CUDA Graph, Triton, TileIR, and CuTe DSL performance optimization workflows.
